Byte-accurate scheduling in a network processor
AssigneeLSI Corporation
InventorsDavid Sonnier, Balakrishnan Sundararaman
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AssigneeLSI Corporation
InventorsDavid Sonnier, Balakrishnan Sundararaman
Estimating the term…
Described embodiments provide for scheduling packets for transmission by a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues the received task in the associated queue, the queue having a corresponding parent scheduler at each of one or more next levels of the scheduling hierarchy up to the root scheduler. Each scheduler determines one or more tasks to schedule from a given queue based on a default packet size of the packet corresponding to the task. The corresponding packet data is read from a shared memory, and, at each corresponding parent scheduler up to the root scheduler, an actual size of the packet data is updated. Scheduling weights of each corresponding parent scheduler are updated based on the actual size of the packet data.
A method of scheduling packets for transmission by a network processor having a plurality of processing modules and at least one shared memory with packet data, the method comprising:
The method of claim wherein the step of updating, at each corresponding parent scheduler at each of one or more next levels of the scheduling hierarchy up to the root scheduler, an actual size of the packet data, comprises:
A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of scheduling packets for transmission by a network processor having a plurality of processing modules and at least one shared memory with packet data, the method comprising:
A network processor comprising:
A method of scheduling packets thy transmission by a network processor having a plurality of processing modules and at least one shared memory with packet data, the method comprising:
A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of scheduling packets for transmission by a network processor having a plurality of processing modules and at least one shared memory with packet data, the method comprising:
A network processor comprising:
Dependencies are inferred from the claim text.
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Using establishment or release of connections between ports: centralised controller, i.e. arbitration or scheduling
Characterised by scheduling criteria: individual queue per connection or flow, e.g. per VC
Queue service order: weighted service order
For service slots or service orders: based on packet size, e.g. shortest packet first
About 4 years 3 months of term left · ends 1 Feb 2031 (estimated)
1. Field of the Invention
The present invention relates to communication systems, in particular, to data caching and coherency maintenance for an accelerated processor architecture for packet networks.
2. Description of the Related Art
Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.
FIG. 1 shows a block diagram of a network processor operating in accordance with exemplary embodiments of the present invention;
FIG. 2 shows a block diagram of a system cache of the network processor of FIG. 1;
Described embodiments of the present invention provide a Modular Traffic Manager (MTM) for a multi-core, multi-threaded network processor.
Table 1 defines a list of acronyms employed throughout this specification as an aid to understanding the described embodiments of the present invention:
TABLE 1 USB Universal Serial Bus FIFO First-In, First-Out SATA Serial Advanced I/O Input/Output Technology Attachment SCSI Small Computer System DDR Double Data Rate Interface SAS Serial Attached SCSI DRAM Dynamic Random Access Memory PCI-E Peripheral Component MMB Memory Manager Interconnect Express Block SRIO Serial RapidIO CPU Central Processing Unit SoC System-on-Chip μP Microprocessor AXI Advanced eXtensible PLB Processor Local Bus Interface AMBA Advanced Micro- MPP Modular Packet controller Bus Processor Architecture PAB Packet Assembly Block AAL5 ATM Adaptation Layer 5 MTM Modular Traffic Manager SED Stream Editor DBC Data Buffer Controller THID Thread Identifier HE Hash Engine PQM Pre-Queue Modifier SENG State Engine FBI Function Bus Interface TID Task Identifier CCL Classification Com- pletion List SCH Scheduler SEM Semaphore Engine SPP Security Protocol PCM Per Context Memory Processor TIL Task Input Logic PDU Protocol Data Unit TCP Transmission Control PIC Packet Integrity Checker Protocol TS Traffic Shaper FSM Finite State Machine PCR Peak Cell Rate MCR Minimum Cell Rate EF Expedited Forwarding AF Assured Forwarding BE Best Effort Forwarding SDWRR Smooth Deficit Weighted Round Robin mutex MUtually EXclusive CRC Cyclic Redundancy Check IP Internet Protocol