Low power deserializer and demultiplexing method
AssigneeQUALCOMM Incorporated
InventorsChulKyu Lee, George Alan Wiley
Life of this patent
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Abstract
A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit streams. The first and second bit streams are respectively serially shifted along a first plurality of shift registers and a second plurality of shift registers. A first portion of the first bit stream in the first plurality of shift registers is selected and a second portion of the second bit stream in the second plurality of shift registers is also selected. A parallel group of data in a parallel data stream is formed from the first and second portions.
Claims28
A deserializer, comprising:
- a first demultiplexer including an input to receive a first serial data stream and first and second outputs to alternatingly output successive bits of the first serial data stream on the first and second outputs;
- first and second plurality of shift registers respectively coupled to the first and second outputs;
- and
- a first selector including a plurality of parallel multiplexers each including a plurality of inputs and a selectable output forming a portion of a first parallel data stream, a first input on one of the plurality of multiplexers couples to the first plurality of shift registers and a second input on the one of the plurality of multiplexers couples to the second plurality of shift registers.
A deserializer, comprising:
- an asynchronous demultiplexer to receive a serial data stream;
- and
- first and second demultiplexers respectively coupled to outputs of the asynchronous demultiplexer, the first and second demultiplexers each include a plurality of shift registers, the first and second demultiplexers further comprising a selector including at least one multiplexer having a first input coupled to a first shift register and a second input coupled to a second, different shift register, the selector further outputs a grouping of a non-base two quantity of data in the parallel data stream.
A method for deserializing a serial bit stream, comprising:
- alternatingly demultiplexing a serial data stream into first and second bit streams;
- respectively serially shifting the first bit stream along a first plurality of shift registers and the second bit stream along a second plurality of shift registers;
- and
- selecting at one input of a multiplexer at least a first portion of the first bit stream from the first plurality of shift registers and at a second input of the multiplexer at least a second portion of the second bit stream from the second plurality of shift registers to form a parallel group of data in a parallel data stream.
A handset, comprising:
- a serializer to generate a serial data stream from a parallel data stream;
- and
- a deserializer to generate the parallel data stream from the serial data stream, the deserializer, including:
- an asynchronous demultiplexer to receive a serial data stream;
- and
- first and second demultiplexers respectively coupled to outputs of the asynchronous demultiplexer, the first and second demultiplexers each include a plurality of shift registers, the first and second demultiplexers further comprising a selector including at least one multiplexer having a first input coupled to a first shift register and a second input coupled to a second, different shift register, the selector to output a non-base two quantity of data in the parallel data stream.
A deserializer for deserializing a serial bit stream, comprising:
- means for alternatingly demultiplexing a serial data stream into first and second bit streams;
- means for respectively serially shifting the first bit stream along a first plurality of shift registers and the second bit stream along a second plurality of shift registers;
- and
- means for selecting at one input of a multiplexer at least a first portion of the first bit stream from the first plurality of shift registers and at a second input of the multiplexer at least a second portion of the second bit stream from the second plurality of shift registers to form a parallel group of data in a parallel data stream.
Dependencies are inferred from the claim text.