On-die termination circuit, memory device, memory module, and method of operating and training an on-die termination

An on-die termination (ODT) circuit, comprising:

• a first termination circuit including a second switch and configured to switchably connect a first termination impedance between an input/output data node and a first power supply voltage;
• a second termination circuit including a second switch and configured to switchably connect a second termination impedance between the input/output data node and the first power supply voltage;
• and
• a switch-control circuit configured to perform a logic operation on an output enable signal (DOEN) and an asynchronous control signal (ACS) to output a first switch-control signal and a second switch-control signal to selectively activate the first termination circuit and the second termination circuit, respectively, to selectively connect the first termination impedance, the second termination impedance, or both the first termination impedance and the second termination impedance between the input/output data node and the first power supply voltage,
• wherein the input/output data node receives data read out or written into a memory device, wherein
• a first total impedance value is connected between the input/output data node and the first power supply voltage during a memory READ mode and based on a first set of predetermined logic levels of DOEN and ACS;
• a second total impedance value, different from the first total impedance value, is connected between the input/output data node and the first power supply voltage during a memory WRITE mode and based on a second set of predetermined logic levels of DOEN and ACS;
• a third total impedance value, different from the first and second total impedance values is connected between the input/output data node and the first power supply voltage during a memory normal mode and based on a third set of predetermined logic levels of DOEN and ACS.

A method of providing termination impedance at an input/output data line of a memory device, comprising:

• performing a logic operation on an output enable (DOEN) signal and an asynchronous control signal (ACS) to output a first switch-control signal configured to selectively activate a first termination circuit having a first termination impedance and to output a second switch-control signal configured to selectively activate a second termination circuit having a second termination impedance,
• wherein the first termination circuit is configured to switchably connect the first termination impedance between the input/output data line and a first power supply voltage,
• wherein the second termination circuit is configured to switchably connect the second termination impedance between the input/output data line and the first power supply voltage,
• wherein the ACS is asynchronous with respect to a clock signal of the memory device and is generated based on the presence of a memory WRITE command,
• wherein the first switch-control signal activates the first termination circuit only if the memory WRITE command is present, and
• wherein the DOEN signal is generated based on the presence of a memory READ command.