Semiconductor memory device and method of controlling the same

A semiconductor device comprising:

• a memory core with a plurality of memory cells;
• an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line;
• and
• a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,
• wherein the internal voltage generator includes a plurality of booster circuits coupled to the low power entry circuit, and a detector, and
• wherein at least one of the plurality of booster circuits is inactivated in response to the low power signal.

A semiconductor device comprising:

• a memory core with a plurality of memory cells;
• an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line;
• and
• a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,
• wherein a voltage, which is lower than the boosted internal voltage, is supplied to the internal power supply line in the low power consumption mode, and
• wherein the internal voltage generator includes a detector and a booster circuit.

A semiconductor device comprising:

• a memory core including a plurality of memory cells;
• an internal voltage generator, coupled to the memory core via an internal power supply line, that generates an internal voltage based on an external voltage and supplies the internal voltage to the memory core via the internal power supply line;
• and
• a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,
• wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and
• wherein the internal voltage generator includes a comparator, a divider circuit and a regulator.

A semiconductor device provided on a substrate comprising:

• an internal voltage generator that generates an internal voltage based on an external voltage and supplies the internal voltage to the substrate via an internal power supply line;
• and
• a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,
• wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and
• wherein the internal voltage generator includes an oscillator and a pumping circuit.

A semiconductor device comprising:

• a bit line coupled to a memory cell;
• an internal voltage generator that generates a precharge voltage based on an external voltage and supplies the precharge voltage to the bit line;
• and
• a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,
• wherein the internal voltage generator, stops supplying the precharge voltage to the bit line in response to the low power signal while the external voltage is supplied to the semiconductor device, and
• wherein the internal voltage generator includes a comparator.

A semiconductor device comprising:

• a bit line coupled to a memory cell;
• an internal voltage generator that generates a precharge voltage based on an external voltage and supplies the precharge voltage to the bit line;
• and
• a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,
• wherein the internal voltage generator, coupled to the low power entry circuit, stops supplying the precharge voltage to the bit line in response to the low power signal while the external voltage is supplied to the semiconductor device, and
• wherein the internal voltage generator includes a first comparator unit comparing the precharge voltage with a first reference voltage to output a first comparison signal, a second comparator unit comparing the precharge voltage with a second reference voltage to output a second comparison signal, and a driver circuit, and
• wherein the driver circuit includes a first driver unit operating responsive to the first comparison signal, and a second driver unit operating responsive to the second comparison signal, and
• wherein the precharge voltage is supplied from a common output node of the first and second driver units to the bit line.