Semiconductor memory device incorporating an interface chip for selectively refreshing memory cells in core chips
AssigneeElpida Memory, Inc.
InventorsJunichi Hayashi, Akira Ide
Life of this patent
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Abstract
In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened.
Claims28
A semiconductor memory device comprising:
- a plurality of core chips assigned to mutually different chip information, each of the core chips comprising a plurality of memory cells that require a refresh operation to hold data stored therein;
- and
- an interface chip that receives a refresh command and a first address information supplied from the outside, the first address information relating to the chip information, the interface chip generates at least onetime of a refresh control signal based on the refresh command, and supplies the refresh control signal and the first address information in common to the core chips, wherein
- each of the core chips includes:
- a determining circuit that determines whether the first address information supplied from the interface chip selects a respective core chip;
- and
- a refresh control circuit that performs the refresh operation to the memory cell included in the respective core chip in response to the refresh control signal when the determining circuit determines that the first address information selects the respective core chip.
A memory system comprising:
- a semiconductor memory device comprising a plurality of core chips and an interface chip that controls the core chips, each of the core chips including a plurality of memory cells and a refresh control circuit that performs a refresh operation to the memory cells;
- and
- a memory controller that controls the semiconductor memory device, wherein
- the memory controller includes:
- a first circuit that issues a refresh command at a plurality of times during a predetermined period;
- and
- a second circuit that issues an address information that selects the core chips along with the refresh command,
- the interface chip includes a refresh-control-signal generation circuit that receives the refresh command and the address information that are supplied from the memory controller and generates a refresh control signal in response to the refresh command,
- the interface chip supplies the refresh control signal and the address information in common to the core chips,
- each of the core chips includes a determining circuit that determines whether the address information selects a respective core chip, and
- the refresh control circuit performs the refresh operation to the memory cell in response to the refresh control signal when the address information selects the respective core chip.
Dependencies are inferred from the claim text.