Programmable precharge circuitry

An integrated circuit having a positive power supply line, comprising:

• a data line;
• a plurality of memory cells coupled to the data line;
• a latch circuit that is coupled to the data line and that receives a precharge signal for precharging the data line, wherein the latch circuit includes an intermediate node that is coupled between the positive power supply line and the data line;
• and
• a programmable-strength pull-up circuit that receives the precharge signal and that is coupled between the positive power supply line and the intermediate node, wherein the latch circuit is configured to isolate the programmable-strength pull-up circuit from the data line when the data line is less than an intermediate threshold voltage level and is configured to electrically couple the programmable-strength pull-up circuit to the data line when the data line exceeds the intermediate threshold voltage level.

An integrated circuit having a positive power supply line, comprising:

• a data line;
• a plurality of memory cells connected to the data line;
• a latch circuit connected to the data line, wherein the latch circuit includes first and second series-connected n-channel metal-oxide-semiconductor (NMOS) transistors and a latch inverter, wherein the latch inverter has an input that is connected to the data line and an output, wherein the first NMOS transistor has a first gate terminal connected to the output, and wherein the second NMOS transistor has a second gate terminal controlled by a precharge signal;
• and
• programmable-strength precharge circuitry coupled between the positive power supply line and the data line, wherein the programmable-strength precharge circuitry includes groups of precharge circuits that are coupled in parallel and that are controlled by the precharge signal, and wherein at least one of the groups of precharge circuits charges the data line.