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US 8,619,481 B2Granted
Switched interface stacked-die memory architecture
AssigneeMicron Technology, Inc.
InventorsJoe M. Jeddeloh, Paul A. LaBerge
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Abstract
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
Claims19
A method comprising:
- receiving a memory request including a requested memory address;
- sending at least one of the memory request or a modified memory request to a selected vault, the modified memory request to include a repair address;
- partially decoding the requested memory address;
- estimating a latency associated with translating the requested memory address to the repair address to derive an estimated latency;
- comparing the estimated latency to a threshold latency value;
- and
- sending the memory request including the requested memory address to the selected vault if the estimated latency is greater than the threshold latency value.
4 more elements
A method comprising:
- decoding a requested memory address;
- estimating a latency associated with translating the requested memory address to a repair address to derive an estimated latency;
- comparing the estimated latency to a threshold latency value;
- and
- sending the requested memory address to a selected vault if the estimated latency is greater than the threshold latency value.
2 more elements
Dependencies are inferred from the claim text.