US 8,619,480 B2 · Method and system for memory controller calibration

Abstract

A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The method may include determining if a second pattern exists in the memory in response to a determination that the unused memory location does not exist. The method may include iteratively modifying a first delay of a first delay control module among a plurality of delay values. The method may include reading from a memory location including the first pattern or the second pattern for each iteration of modification of the first delay. The method may include modifying one or more second delays, each second delay associated with one of one or more second delay control modules, based on the results of reading from the memory location.

Claims18

Dependent claims

A method for calibration of a memory controller, comprising:

determining if an unused memory location exists in a memory;
in response to a determination that the unused memory location exists, writing a first pattern to the unused memory location;
in response to a determination that the unused memory location does not exist, determining if a second pattern exists in the memory;
iteratively modifying a first delay of a first delay control module among a plurality of delay values, the first delay control module configured to delay a clock or data signal by the first delay;
for each iteration of modification of the first delay, reading from a memory location including the first pattern or the second pattern;
and
based on the results of reading from the memory location, modifying one or more second delays, each second delay associated with one of one or more second delay control modules, the one or more second delay control modules each configured to delay the clock or data signal by the one or more second delays.

4 more elements

A memory controller comprising:

one or more first input/output blocks used for normal memory operations, each of the first input/output blocks including a first delay control module having a first delay for delaying a clock or data signal;
an unused memory location monitor configured to monitor usage of one or more memory devices associated with the memory controller and report identities of unused memory locations;
a pattern monitor configured to:
monitor data written to the one or more memory devices as a result of write operations;
and
if data written to the one or more memory devices matches a first pattern, report the memory location of the first pattern;
and
a second input/output block including a second delay control module having a second delay;
a dynamic calibration controller communicatively coupled to the unused memory location monitor and the pattern monitor and configured to:
if the unused memory location reports the identity of an unused memory location, write a second pattern to the unused memory location;
if the unused memory location reports no unused memory locations exist, determine if the first pattern exists in memory;
iteratively modify the second delay among a plurality of delay values;
for each iteration of modification of the second delay, read from a memory location including the first pattern or the second pattern via the second input/output block;
and
based on the results of reading from the memory location, modifying the first delay of the first delay control module of each of the first input/output blocks.

12 more elements

A computing device comprising:

a processor;
a memory system communicatively coupled to the processor, the memory system comprising:
one or more memory devices configured to retain program instructions or data for a period of time;
and
a memory controller communicatively coupled to the one or more memory devices, the memory controller comprising:
one or more first input/output blocks used for normal memory operations, each of the first input/output blocks including a first delay control module having a first delay for delaying a clock or data signal;
an unused memory location monitor configured to monitor usage of the one or more memory devices and report identities of unused memory locations;
a pattern monitor configured to:
monitor data written to the one or more memory devices as a result of write operations;
and
if data written to the one or more memory devices matches a first pattern, report the memory location of the first pattern;
and
a second input/output block including a second delay control module having a second delay;
a dynamic calibration controller communicatively coupled to the unused memory location monitor and the pattern monitor and configured to:
if the unused memory location reports the identity of an unused memory location, write a second pattern to the unused memory location;
if the unused memory location reports no unused memory locations exist, determine if the first pattern exists in memory;
iteratively modify the second delay among a plurality of delay values;
for each iteration of modification of the second delay, read from a memory location including the first pattern or the second pattern via the second input/output block;
and
based on the results of reading from the memory location, modifying the first delay of the first delay control module of each of the first input/output blocks.

17 more elements

Dependencies are inferred from the claim text.

Method and system for memory controller calibration

Life of this patent

Method and system for memory controller calibration

Life of this patent

Abstract

Claims18