Two-port SRAM write tracking scheme
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsBing Wang, Kuoyuan (Peter) Hsu, Derek C. Tao
Life of this patent
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Abstract
A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.
Claims20
A Static Random Access Memory (SRAM), comprising:
- at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL), the at least two memory cells being inside a cell array of the SRAM and each memory cell being coupled to a respective read word line (RWL) and a respective write word line (WWL);
- and
- a write tracking control circuit coupled by the RBL or the WBL to the at least two memory cells for determining a write time of the at least two memory cells,
- wherein the write tracking control circuit is capable of receiving an input voltage and providing an output voltage, and the respective RWL and the respective WWL of each memory cell of the at least two memory cells are assertable during a write tracking operation.
A method for a Static Random Access Memory (SRAM), comprising:
- writing the same data simultaneously to at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL) for a write tracking operation, the at least two memory cells being inside a cell array of the SRAM;
- reading the data written to the at least two memory cells from the RBL;
- and
- determining a write time of the SRAM using a write tracking control circuit coupled by the RBL or the WBL to the at least two memory cells.
A Static Random Access Memory (SRAM), comprising:
- at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL), each memory cell coupled to a respective read word line (RWL) and a respective write word line (WWL);
- and
- a write tracking control circuit coupled to the at least two memory cells for determining a write time of the at least two memory cells, the write tracking control circuit including a first PMOS transistor configured to precharge the WBL and a second PMOS transistor configured to precharge the RBL,
- wherein the write tracking control circuit is capable of receiving an input voltage, the input voltage for writing to the at least two memory cells simultaneously during a write tracking operation, and providing an output voltage based on a read voltage of the RBL coupled to the at least two memory cells during the write tracking operation, and the respective RWL and the respective WWL of each memory cell of the at least two memory cells are assertable during a write tracking operation.
Dependencies are inferred from the claim text.