Semiconductor memory apparatus comprising a nonvolatile memory cell and method of operating the same
AssigneeHynix Semiconductor Inc.
InventorGyo Soo Chu
Life of this patent
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Abstract
A semiconductor memory apparatus includes a memory block including memory strings having respective channel layers coupled between respective bit lines and a source line, an operation circuit group configured to supply hot holes to the channel layers and to perform an erase operation on memory cells of the memory strings, an erase operation determination circuit configured to generate a block erase enable signal when hot holes of at least a target number are supplied to a first channel layer of the channel layers, and a control circuit configured to perform the erase operation in response to the block erase enable signal.
Claims20
A semiconductor memory apparatus, comprising:
- a memory block including memory strings having respective channel layers coupled between respective bit lines and a source line;
- an operation circuit group configured to supply hot holes to the channel layers and to perform an erase operation on memory cells of the memory strings;
- an erase operation determination circuit configured to determine whether hot holes of a target number are injected into a first channel layer of the channel layers and generate a block erase enable signal for erasing the memory cells when the hot holes of at least the target number are supplied to the first channel layer;
- and
- a control circuit configured to control a point of time where the operation circuit group performs the erase operation in response to the block erase enable signal.
A method of operating a semiconductor memory apparatus, comprising:
- supplying hot holes to channel layers of memory strings coupled between respective bit lines and a source line;
- determining whether hot holes of a target number are infected into the channel layers;
- and
- performing an erase operation on memory cells of the memory strings when hot holes of at least the target number have been supplied to the channel layers.
Dependencies are inferred from the claim text.