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US 8,619,474 B2Granted
Data line management in a memory device
AssigneeMicron Technology, Inc.
InventorsAkira Goda, Andrew Bicksler, Violante Moschiano, Giuseppina Puzzilli
Life of this patent
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Abstract
Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.
Claims40
A method of operating a memory device having a plurality of memory cells, the method comprising:
- enabling one or more memory cells to be programmed;
- biasing a first portion of data lines of a plurality of data lines to a first program inhibit voltage, where the first portion of data lines are coupled to memory cells to be inhibited from programming, and applying a first plurality of programming pulses to the enabled memory cells while biasing the first portion of data lines to the first program inhibit voltage;
- and
- biasing a second portion of data lines of the plurality of data lines to a second program inhibit voltage, where the second portion of data lines are coupled to memory cells to be inhibited from programming, and applying a second plurality of programming pulses to the enabled memory cells while biasing the second portion of data lines to the second program inhibit voltage;
- wherein the second program inhibit voltage is greater than the first program inhibit voltage and where the second plurality of programming pulses are applied following the first plurality of programming pulses;
- wherein a particular programming pulse of the first plurality of programming pulses has a voltage level greater than a preceding programming pulse of the first plurality of programming pulses;
- and
- wherein a particular programming pulse of the second plurality of programming pulses has a voltage level greater than a preceding programming pulse of the second plurality of programming pulses.
5 more elements
A method of programming a memory device having a plurality of memory cells, the method comprising:
- biasing one or more data lines of a plurality of data lines, the one or more data lines being coupled to memory cells not selected for programming, to a first program inhibit voltage, and applying a first plurality of programming pulses to memory cells selected for programming while biasing the one or more data lines of the plurality of data lines to the first program inhibit voltage;
- and
- biasing all data lines of the plurality of data lines to a second program inhibit voltage, discharging data lines of the plurality of data lines that are coupled to memory cells selected for programming, and applying a second plurality of programming pulses to the selected memory cells while biasing remaining data lines of the plurality of data lines to the second program inhibit voltage;
- wherein the second program inhibit voltage is greater than the first program inhibit voltage and where the second plurality of programming pulses are applied following the first plurality of programming pulses;
- wherein a particular programming pulse of the first plurality of programming pulses has a voltage level greater than a preceding programming pulse of the first plurality of programming pulses;
- and
- wherein a particular programming pulse of the second plurality of programming pulses has a voltage level greater than a preceding programming pulse of the second plurality of programming pulses.
4 more elements
A method of programming a memory device having a plurality of memory cells logically arranged in rows and in columns where each row is coupled to an access line and each column is coupled to a data line, the method comprising:
- performing a first programming operation wherein the first programming operation comprises biasing one or more data lines to a first program inhibit voltage and applying a first plurality of programming pulses to a selected row where the first programming operation is repeated for a first number of iterations prior to changing to performing a second programming operation, and where the one or more data lines are biased to the first program inhibit voltage while applying the first plurality of programming pulses to the selected row;
- and
- performing the second programming operation wherein the second programming operation comprises biasing one or more data lines to a second program inhibit voltage and applying a second plurality of programming pulses to the selected row where the second programming operation is repeated for a second number of iterations, and where the one or more data lines are biased to the second program inhibit voltage while applying the second plurality of programming pulses to the selected row;
- wherein the second program inhibit voltage is greater than the first program inhibit voltage;
- wherein a particular programming pulse of the first plurality of programming pulses has a voltage level greater than a preceding programming pulse of the first plurality of programming pulses;
- and
- wherein a particular programming pulse of the second plurality of programming pulses has a voltage level greater than a preceding programming pulse of the second plurality of programming pulses.
4 more elements
A memory device, comprising:
- a plurality of memory cells;
- and
- control circuitry, wherein the control circuitry is configured to perform a first program operation wherein the first program operation comprises a first program inhibit bias applied to one or more data lines and the application of a first plurality of program pulses to selected memory cells while applying the first program inhibit bias to the one or more data lines, perform a second program operation wherein the second program operation comprises a second program inhibit bias applied to one or more data lines and the application of a second plurality of program pulses to the selected row while applying the second program inhibit bias to the one or more data lines, where the first program operation is performed prior to the second program operation and where the second program inhibit voltage is greater than the first program inhibit voltage;
- wherein the first program operation is repeated for a first number of iterations and where the second program operation is repeated for a second number of iterations;
- wherein a particular programming pulse of the first plurality of programming pulses has a voltage level greater than a preceding programming pulse of the first plurality of programming pulses;
- and
- wherein a particular programming pulse of the second plurality of programming pulses has a voltage level greater than a preceding programming pulse of the second plurality of programming pulses.
4 more elements
A memory device configured to:
- apply a first program inhibit bias to data lines during a first portion of a program operation;
- and
- apply a second program inhibit bias to data lines during a second portion of the program operation, wherein the second program inhibit bias is greater than the first program inhibit bias;
- wherein the first portion of the program operation comprises an application of a first plurality of program pulses while applying the first program inhibit bias;
- wherein the second portion of the program operation comprises an application of a second plurality of program pulses while applying the second program inhibit bias;
- wherein a particular programming pulse of the first plurality of programming pulses has a voltage level greater than a preceding programming pulse of the first plurality of programming pulses;
- and
- wherein a particular programming pulse of the second plurality of programming pulses has a voltage level greater than a preceding programming pulse of the second plurality of programming pulses.
5 more elements
A method for programming a memory device, comprising:
- applying a first plurality of program pulses while applying a first program inhibit voltage to inhibit a data line while data line to data line capacitance is at a particular level;
- and
- applying a second plurality of program pulses while applying a second program inhibit voltage to the data line while the data line to data line capacitance comprises a level which is lower than the particular level.
A method of programming a memory device having a plurality of memory cells, the method comprising:
- biasing each data line of a plurality of data lines to a first program inhibit voltage where each data line is coupled to one or more memory cells of the plurality of memory cells;
- followed by discharging data lines of the plurality of data lines that are coupled to memory cells selected for programming and applying a first plurality of programming pulses to the selected memory cells while biasing remaining data lines of the plurality of data lines to the first program inhibit voltage;
- and
- biasing each data line of the plurality of data lines to a second program inhibit voltage followed by discharging data lines of the plurality of data lines that are coupled to memory cells selected for programming and applying a second plurality of programming pulses to the selected memory cells while biasing remaining data lines of the plurality of data lines to the second program inhibit voltage;
- wherein a particular programming pulse of the first plurality of programming pulses has a voltage level greater than a preceding programming pulse of the first plurality of programming pulses;
- and
- wherein a particular programming pulse of the second plurality of programming pulses has a voltage level greater than a preceding programming pulse of the second plurality of programming pulses.
4 more elements
Dependencies are inferred from the claim text.