US 8,619,469 B2 · FTP memory device with programming and erasing based on Fowler-Nordheim effect

Abstract

An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are coupled in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate.

Claims48

Dependent claims

A non-volatile memory device integrated in a chip of semiconductor material, the memory device comprising:

a plurality of memory cells, each one including a first well and a second well of a first type of conductivity being formed in an insulating region of a second type of conductivity;
a first, a second, a third and a fourth region of the second type of conductivity being formed in the first well for defining a sequence of a first selection transistor of MOS type;
a storage transistor of floating gate MOS type;
and
a second selection transistor of MOS type being coupled in series, the first region being short-circuited to the first well, a first gate of the first selection transistor, a second gate of the second selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well, the control gate being capacitively coupled with the floating gate.

2 more elements

A memory array, comprising:

a first bit line;
first and second access-control lines;
a first word line;
a first program-erase line;
and
a first non-volatile memory cell, comprising:
a storage transistor having a floating gate capacitively coupled to the first word line, a body coupled to the first program-erase line, and first and second conduction nodes;
a first access transistor having a gate coupled to the first access-control line, a body coupled to the first program-erase line, a first conduction node coupled to the first bit line, and a second conduction node coupled to the first conduction node of the storage transistor;
and
a second access transistor having a gate coupled to the second access-control line, a body coupled to the first program-erase line, a first conduction node coupled to the second conduction node of the storage transistor, and a second conduction node coupled to the first program-erase line.

7 more elements

Dependencies are inferred from the claim text.

FTP memory device with programming and erasing based on Fowler-Nordheim effect

Life of this patent

FTP memory device with programming and erasing based on Fowler-Nordheim effect

Life of this patent

Abstract

Claims48