Nonvolatile latch circuit, nonvolatile flip-flop circuit, and nonvolatile signal processing device

A nonvolatile latch circuit comprising:

• a first logic inversion circuit;
• a second logic inversion circuit having an input terminal connected to an output terminal of the first logic inversion circuit and an output terminal connected to an input terminal of the first logic inversion circuit;
• a first transistor which includes a first terminal, a second terminal, and a first control terminal, and controls a conduction state between the first terminal and the second terminal in accordance with a voltage of the first control terminal;
• a second transistor which includes a third terminal, a fourth terminal, and a second control terminal, and controls a conduction state between the third terminal and the fourth terminal in accordance with a voltage of the second control terminal;
• a variable resistance element which has a structure in which an oxide layer including an oxygen-deficient transition metal oxide is interposed between first and second electrodes, and which changes to a first resistance state under application of a first application voltage higher in absolute value than a predetermined first voltage so as to cause a current to flow in a direction from the first electrode to the second electrode, and changes to a second resistance state under application of a second application voltage higher in absolute value than a predetermined second voltage so as to cause a current to flow in a direction from the second electrode to the first electrode, the second resistance state being a state in which the variable resistance element has a resistance value larger than a resistance value in the first resistance state;
• a summing amplifier circuit which detects a sum value of a potential at a first node and a potential at a second node when a read voltage lower in absolute value than the first voltage and the second voltage is applied to each of the control terminals of the first and second transistors, the first node being a connection point between the first terminal and the first electrode, and the second node being a connection point between the fourth terminal and the second electrode;
• and
• a third logic inversion circuit which inverts an output of the summing amplifier circuit,
• wherein the output terminal of the first logic inversion circuit and the second terminal of the first transistor are connected to each other via a third node, and the output terminal of the second logic inversion circuit and the third terminal of the second transistor are connected to each other via a fourth node,
• an absolute value of a first current that flows through the variable resistance element when the variable resistance element is caused to change from the second resistance state to the first resistance state is smaller than an absolute value of a second current that flows through the variable resistance element when the variable resistance element is caused to change from the first resistance state to the second resistance state,
• the variable resistance element immediately after being manufactured is in a third resistance state, and when a third application voltage higher than the first application voltage is applied so as to cause a current to flow in a direction from the first electrode to the second electrode, the variable resistance element changes from the third resistance state to a fourth resistance state, the third resistance state being a state in which the variable resistance element has a resistance value larger than the resistance value in the second resistance state, and the fourth resistance state being a state in which the variable resistance element has a resistance value smaller than or equal to the resistance value in the first resistance state, and
• the summing amplifier circuit detects the third resistance state, and when the detected output is inputted to the third node or the fourth node via the third logic inversion circuit, states of the first logic inversion circuit and the second logic inversion circuit are each set to a state that is needed in order to cause a resistance value of the variable resistance element to change from the third resistance state to the fourth resistance state.