8-transistor SRAM cell design with inner pass-gate junction diodes

A memory device comprising:

• a plurality of 8-transistor SRAM cells arranged in columns and rows, with each 8-transistor SRAM cell comprising:
• two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit;
• first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line, the first and second pass-gate transistors each having an active region and a diffusion area shared with one of the pull-down transistors;
• an inner junction diode at each shared diffusion area between one of the pass-gate transistors and one of the pull-down transistors to block charge transfer from the write bit line into the cell;
• and
• first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line;
• wherein the 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state while the first and second read transistors affect the signal asserted during the read operation on the read bit line coupled to the cell.

An integrated circuit comprising:

• a memory device comprising:
• a plurality of 8-transistor SRAM cells arranged in columns and rows, with each 8-transistor SRAM cell comprising:
• two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit;
• first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line, the first and second pass-gate transistors each having an active region and a diffusion area shared with one of the pull-down transistors;
• an inner junction diode at each shared diffusion area between one of the pass-gate transistors and one of the pull-down transistors to block charge transfer from the write bit line into the cell;
• and
• first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line;
• wherein the 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state while the first and second read transistors affect the signal asserted during the read operation on the read bit line coupled to the cell.