Static random-access memory having read circuitry with capacitive storage

Memory element circuitry, comprising:

• a bistable data storage element;
• a read data line;
• a write data line;
• an address line;
• read circuitry coupled between the bistable data storage element and the read data line, wherein the read circuitry includes a data storage node, a temporary passive memory element coupled to the data storage node, a first transistor having a first source-drain terminal that is coupled to the bistable data storage element and a second source-drain terminal that is coupled to the data storage node, a second transistor having a first source-drain terminal that is coupled to the data storage node and a second source-drain terminal that is coupled to the read data line, wherein the first and second transistors have gates that are coupled to the address line, and wherein the temporary passive memory element is operable to temporarily store data from the bistable data storage element on the data storage node;
• and
• write circuitry coupled between the bistable data storage element and the write data line.

A method of operating memory element circuitry having a bistable data storage element that is coupled to a bit line by read circuitry that includes a data storage node coupled to a temporary memory element, comprising:

• supplying data from the bistable data storage element to the data storage node during a read operation, wherein the read operation outputs the data to the bit line, wherein the read operation comprises:
• when a read address signal is deasserted, passing the data from the bistable data storage element to the data storage node via a first transistor in the read circuitry;
• and
• when the read address signal is asserted, outputting the data to the bit line via a second transistor in the read circuitry.