Adaptive write bit line and word line adjusting mechanism for memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHank Cheng, Ming-Zhang Kuo, Chung-Cheng Chou
Life of this patent
Estimating the term…
Abstract
A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.
Claims20
A memory, comprising:
- a capacitor coupled to a write bit line or a word line;
- an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line;
- a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse;
- wherein the capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node, the boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.
A boost circuit, comprising:
- a capacitor coupled to a write bit line or a word line;
- an initializer configured to pre-charge a first node between the capacitor and the write bit line or the word line;
- and
- a controllable initial level adjuster configured to adjust a voltage level of the pre-charged first node in response to a pulse,
- wherein the capacitor is configured to receive a boost signal at a second node at a terminal opposite the first node, the boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.
A method of biasing a write bit line or a word line, the method comprising:
- pre-charging a first node at a first terminal of a capacitor to a pre-charged voltage level using an initializer, wherein the capacitor is coupled to the write bit line or the word line;
- adjusting a voltage level of a second node using a controllable initial level adjuster;
- supplying a boost signal to a third node to a second terminal of the capacitor opposite the first terminal to bias a voltage level of the write bit line lower or bias the word line.
Dependencies are inferred from the claim text.