Nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorKei Sakamoto
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory device includes a memory cell array including cells provided at each of intersections of first and second lines and each having a variable resistance element and a first diode connected in series; a first line control circuit for supplying voltages to the first lines; and a second line control circuit for supplying voltages to the second lines, the cells each having one of the second lines connected to an anode side of the first diode and one of the first lines connected to a cathode side of the first diode, and the memory cell array including a second diode inserted in each of the second lines between the second line control circuit and the cells and each having a side of the second line control circuit as an anode and a side of the cells as a cathode.
Claims20
A nonvolatile semiconductor memory device, comprising:
- a memory cell array including a plurality of first lines and second lines intersecting each other and a plurality of memory cells provided at each of intersections of the plurality of first lines and second lines and each having a variable resistance element and a first diode connected in series;
- a first line control circuit for supplying a selected first line voltage to a selected first line among the first lines that is connected to a selected access target memory cell among the memory cells, and supplying an unselected first line voltage to an unselected first line among the first lines other than the selected first line;
- and
- a second line control circuit for supplying a selected second line voltage to a selected second line among the second lines that is connected to the selected access target memory cell, and supplying an unselected second line voltage to an unselected second line among the second lines other than the selected second line,
- the memory cells each having one of the second lines connected to an anode side of the first diode and one of the first lines connected to a cathode side of the first diode, and
- the memory cell array including a second diode which is inserted in each of the second lines between the second line control circuit and the memory cells and has a side of the second line control circuit as an anode and a side of the memory cells as a cathode.
A nonvolatile semiconductor memory device, comprising:
- a memory cell array including a plurality of first lines and second lines intersecting each other and a plurality of memory cells provided at each of intersections of the plurality of first lines and second lines and each having a variable resistance element and a first diode connected in series;
- a first line control circuit for supplying a selected first line voltage to a selected first line among the first lines that is connected to a selected access target memory cell among the memory cells, and supplying an unselected first line voltage to an unselected first line among the first lines other than the selected first line;
- and
- a second line control circuit for supplying a selected second line voltage to a selected second line among the second lines that is connected to the selected access target memory cell, and supplying an unselected second line voltage which is lower than the unselected first line voltage to an unselected second line among the second lines other than the selected second line,
- the memory cells each having one of the second lines connected to an anode side of the first diode and one of the first lines connected to a cathode side of the first diode, and
- the memory cell array including a second diode which is inserted in each of the second lines between the second line control circuit and the memory cells and has a side of the second line control circuit as an anode and a side of the memory cells as a cathode.
A nonvolatile semiconductor memory device, comprising:
- a memory cell array including a plurality of first lines and second lines intersecting each other and a plurality of memory cells provided at each of intersections of the plurality of first lines and second lines and each having a variable resistance element and a first diode connected in series;
- a first line control circuit for supplying a selected first line voltage to a selected first line among the first lines that is connected to a selected access target memory cell among the memory cells, and supplying an unselected first line voltage to an unselected first line among the first lines other than the selected first line;
- and
- a second line control circuit for supplying a selected second line voltage to a selected second line among the second lines that is connected to the selected access target memory cell, and supplying an unselected second line voltage which is lower than the unselected first line voltage to an unselected second line among the second lines other than the selected second line,
- the memory cell array including a second diode which is inserted in each of the second lines between the second line control circuit and the memory cells and has a side of the second line control circuit as an anode and a side of the memory cells as a cathode.
Dependencies are inferred from the claim text.