Memory arrays and associated methods of manufacturing
AssigneeMicron Technology, Inc.
InventorJun Liu
Life of this patent
Estimating the term…
Abstract
Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction. The first and second contact lines are generally parallel to each other. The memory array also includes a memory node that includes a first memory cell electrically connected between the access line and the first contact line to form a first circuit, and a second memory cell electrically connected between the access line and the second contact line to form a second circuit different from the first circuit.
Claims24
A memory structure, comprising:
- an access line extending along a first direction;
- a first contact line and a second contact line extending along a second direction different than the first direction, the first and second contact lines being generally parallel to each other;
- a memory node including:
- a first memory cell electrically connected between the access line and the first contact line to form a first circuit;
- a second memory cell electrically connected between the access line and the second contact line to form a second circuit electrically independent from the first circuit;
- and
- a rectifier device between the access line and the first and second memory cells,
- wherein the first and second circuits include a common circuit path through at least a portion of the rectifier device.
A memory structure, comprising:
- a plurality of access lines extending along a first direction;
- a plurality of contact lines extending along a second direction different from the first direction, the individual contact lines and the individual access lines forming a plurality of pairs of access and contact lines;
- a plurality of memory nodes electrically connected to the access and contact lines, the individual memory nodes including:
- a rectifier device including a first junction device and second junction device, wherein the first junction device includes a first doping region arranged with a second doping region to define a first junction, and wherein the second junction device includes a third doping region arranged with the second doping region to define a second junction;
- a first memory cell electrically connected between a first pair of access and contact lines with the rectifier device between the first pair of access lines and the first memory cell;
- and
- a second memory cell electrically connected between a second pair of access and contact lines with the rectifier device between the second pair of access lines and the second memory cell, the first and second pairs of access and contact lines are electrically isolated from each other, wherein the first and second memory cells are connected to the rectifier device, the same access line, and adjacent contact lines.
A memory structure, comprising:
- a plurality of access lines extending along a first direction;
- a plurality of contact lines extending along a second direction that is non-orthogonal to the first direction such that the contact lines are canted relative to the access lines, the individual contact lines and the individual access lines forming a plurality of pairs of access and contact lines;
- a plurality of memory nodes electrically connected to the access and contact lines, the individual memory nodes including:
- two back-to-back junction devices that share a common doping region;
- a first memory cell electrically connected between a first access line and a first contact line with the common doping back-to-back junction devices between the first access line and the first memory cell;
- and
- a second memory cell electrically connected between the first access line and a second contact line with the common doping region of the two back-to-back junction devices between the first access line and the second memory cell.
Dependencies are inferred from the claim text.