Three dimensional non-volatile storage with dual gate selection of vertical bit lines
AssigneeSanDisk 3D LLC
InventorRoy E. Scheuerlein
Life of this patent
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Abstract
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
Claims20
A non-volatile storage system, comprising:
- a substrate;
- a monolithic three dimensional memory array of memory cells positioned above and not in the substrate;
- a plurality of word lines connected together and connected to a subset of the memory cells;
- a plurality of global bit lines;
- a plurality of vertically oriented bit lines connected to the memory cells, the memory cells in combination with the vertically oriented bit lines and the word lines form a continuous mesh;
- a plurality of double gated vertically oriented select devices that are above and not in the substrate, the double gated vertically oriented select devices are connected to the vertically oriented bit lines and the global bit lines, when the double gated vertically oriented select devices are activated the vertically oriented bit lines are in communication with the global bit lines;
- and
- a plurality of select lines connected to both gates of the double gated vertically oriented select devices, each vertically oriented select device is connected to two of the select lines so that both of the two select lines must diving an “on” signal for the respective double gated vertically oriented select devices to be activated.
A method of operating a storage system comprising a monolithic three dimensional memory array of memory cells positioned above and not in an associated substrate, the memory cells are arranged in blocks, vertically oriented bit lines and word lines are connected to the memory cells, the method comprising:
- applying an unselected word line voltage to unselected word lines;
- applying one or more selected bit line voltages to global bit lines based on a data pattern, vertically oriented bit lines and global bit lines are connected to double gated vertically oriented select devices;
- applying one or more selection signals to row select lines on two sides of a particular vertically oriented bit line to activate a respective double gated vertically oriented select device connected to the particular vertically oriented bit line in order to put the particular vertically oriented bit line in communication with a respective global bit line;
- and
- applying a selected word line voltage to a selected word line that is connected to a selected memory cell, the selected memory cell is also connected to the particular vertically oriented bit line, the applying the selected word line voltage and the applying one or more selected bit line voltages causes the selected memory cell to experience a memory operation.
A method of operating a storage system comprising a monolithic three dimensional memory array of memory cells, vertically oriented bit lines and word lines are connected to the memory cells, the method comprising:
- driving signals on word lines and global bit lines;
- using row select line drivers to apply signals on row select lines;
- activating a plurality of select devices based activated signals applied to row select lines on two gate interfaces of each of the plurality of select devices;
- and
- communicating signals from the global bit lines to vertically oriented bit lines above and not in the substrate using the select device in order to perform a memory operation.
Dependencies are inferred from the claim text.