Methods and apparatus of stacking DRAMs

A method for controlling a memory device comprising a plurality of dynamic random access memory (“DRAM”) integrated circuits, the method comprising:

• providing an interface between the plurality of DRAM integrated circuits and a memory bus by buffering at least one of address, control or data signals so as to isolate electrical loads of the plurality of DRAM integrated circuits from the memory bus;
• and
• performing conversion between signal timing of a first protocol at the memory bus and signal timing of a second protocol for accessing at least one of the plurality of DRAM integrated circuits;
• tracking addresses of “m” previous reads;
• and
• comparing the address of a current read with the tracked addresses of the “m” previous reads.

A memory device comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits stacked in a vertical direction;
• and
• a buffer integrated circuit for providing an interface between the plurality of DRAM integrated circuits and a memory bus by buffering at least one of address, control or data signals so as to isolate electrical loads of the plurality of DRAM integrated circuits from the memory bus, wherein the buffer integrated circuit is configured to perform conversion between signal timing of a first protocol at the memory bus and signal timing of a second protocol for accessing at least one of the plurality of DRAM integrated circuits,
• wherein the buffer integrated circuit is configured to track errors and to execute a read operation to a mirrored memory set based on one or more of the tracked errors.

A memory device comprising:

• a plurality of dynamic random access memory (“DRAM”) integrated circuits stacked in a vertical direction;
• and
• a buffer integrated circuit for providing an interface between the plurality of DRAM integrated circuits and a memory bus by buffering at least one of address, control or data signals so as to isolate electrical loads of the plurality of DRAM integrated circuits from the memory bus, wherein the buffer integrated circuit is configured to perform conversion between signal timing of a first protocol at the memory bus and signal timing of a second protocol for accessing at least one of the plurality of DRAM integrated circuits,
• wherein said stacked DRAM integrated circuits comprise p+q DRAM integrated circuits, wherein “p” DRAM integrated circuits comprise a number of DRAM integrated circuits used as a working pool of memory integrated circuits, and wherein “q” DRAM integrated circuits comprise a number of DRAM integrated circuits used as a mirrored pool of memory integrated circuits, wherein “p” and “q” comprise integer values,
• wherein the buffer integrated circuit is configured to track addresses of “m” previous reads, compare an address of a current read with the tracked addresses of the “m” previous reads, and if the buffer integrated circuit detects a match between the address of the current read and one or more of the tracked addresses of the “m” previous reads, read contents from a memory location in the mirrored pool that corresponds to the address of the current read.