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US 8,619,398 B1Granted
ESD protection for differential output pairs
AssigneeAltera Corporation
InventorsAntonio Gallerano, Charles Y. Chu, Jeffrey T. Watt
Life of this patent
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AssigneeAltera Corporation
InventorsAntonio Gallerano, Charles Y. Chu, Jeffrey T. Watt
Estimating the term…
In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.
A differential output circuit with electrostatic discharge (ESD) protection comprising:
A differential output circuit with electrostatic discharge (ESD) protection comprising:
A differential output circuit with electrostatic discharge (ESD) protection comprising:
A differential output circuit with electrostatic discharge (ESD) protection comprising:
A method of providing electrostatic discharge (ESD) protection of a circuit comprising first and second MOS transistors, each having a body in which are formed source and drain regions and a gate, the source regions being connected together at a first node, said method comprising the steps of:
Dependencies are inferred from the claim text.