Non-linear power management device for input power protection
AssigneeFairchild Semiconductor Corporation
InventorAdrian Mikolajczak
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AssigneeFairchild Semiconductor Corporation
InventorAdrian Mikolajczak
Estimating the term…
In one general aspect, an apparatus can include a non-linear power management device having an output terminal configured to be coupled to an output shunt device configured to shunt energy in response to a voltage across the output shunt device exceeding a trigger voltage of the output shunt device. The non-linear power management device can be configured to change to a saturation mode in response to a first current associated with an energy pulse through the non-linear power management device. The apparatus can include an input shunt device coupled to an input terminal of the non-linear power management device and having a trigger voltage higher than the trigger voltage of the output shunt device. The input shunt device can be configured to shunt a second current associated with the energy pulse in response to a voltage drop across the non-linear power management device.
An apparatus, comprising:
A method, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.
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Adapted to a particular application and not provided for elsewhere: responsive to excess voltage appearing at terminals of integrated circuits
Emergency protective circuit arrangements
About 5 years 5 months of term left · ends 15 Mar 2032 (estimated)
This description relates to an input power port protection device.
Input power ports and/or related components can be protected from undesirable power conditions (e.g., electrostatic discharge (ESD)) using multiple external (e.g., off-board) and/or internal (e.g., on-board) discrete devices such as shunt devices (e.g., zener diodes, TVS devices). When the input power port is protected from undesirable power conditions using multiple devices, unpredictable and/or unwanted interactions can occur between the external and/or internal devices. For example, mismatches between external shunt protection devices added to an integrated circuit, which already includes an internal shunt protection device, can result in unpredictable and/or unwanted interactions in the event of an ESD pulse. Specifically, an internal shunt protection device that has a lower trigger voltage may absorb all energy of the ESD pulse, rendering the external shunt protection devices irrelevant, independent of its “power rating”. In some embodiments, the external and internal shunt protection devices may share the energy of the ESD pulse in some fashion that may or may not protect the integrated circuit. Designing matched internal and external shunt protection devices to avoid many of these issues can be a time-consuming, expensive, and/or trial-and-error process, which may not be feasible in some applications. In addition, common methods of balancing (e.g., adding a series resistor) can have an undesirable level of series resistance during normal operation that can cause, for example, signal attenuation. Thus, a need exists for systems, methods, and apparatus to address the shortfalls of present technology and to provide other new and innovative features.
In one general aspect, an apparatus can include a non-linear power management device having an output terminal configured to be coupled to an output shunt device configured to shunt energy in response to a voltage across the output shunt device exceeding a trigger voltage of the output shunt device. The non-linear power management device can be configured to change to a saturation mode in response to a first current associated with an energy pulse through the non-linear power management device. The apparatus can include an input shunt device coupled to an input terminal of the non-linear power management device and having a trigger voltage higher than the trigger voltage of the output shunt device. The input shunt device can be configured to shunt a second current associated with the energy pulse in response to a voltage drop across the non-linear power management device.
FIG. 1A is a block diagram that illustrates an external portion and an internal portion of an input power protection device.
FIG. 1B is a graph that illustrates an example current-voltage (I-V) characteristic of the power management device shown in FIG. 1A.
FIG. 1C is a graph that illustrates another example current-voltage (I-V) characteristic of a power management device such as the power management device shown in FIG. 1A.
FIG. 1A is a block diagram that illustrates an external portion 10 and an internal portion 20 of an input power protection device 100. The input power protection device 100 includes input shunt device 110 and output shunt device 130. As shown in FIG. 1A, a power management device 120 is serially coupled between the input shunt device 110 and the output shunt device 130. In this embodiment, the input shunt device 110 and the power management device 120 are included in the external portion 10 of the input power protection device 100, and the output shunt device 130 is included in the internal portion 20 of the input power protection device 100. In some embodiments, the power management device 120 can be referred to as a non-linear current device or as a current ballast device. In some embodiments, the input shunt device 110, the power management device 120, and/or the output shunt device 130 can collectively be referred to as components of the input power protection device 100.
The internal portion 20 of the input power protection device 100 can be referred to as an internal portion because the components of the internal portion 20 are included in (e.g., integrated within) an integrated circuit (IC) of a device (e.g., a computing device) (not shown). The external portion 10 of the input power protection device 100 can be referred to as an external portion because the components of the external portion 10 are coupled to (e.g., added to) the internal portion 20 and may not be integrated into the integrated circuit including the internal portion 20. Thus, the components of the external portion 10 may be included in a device (e.g., discrete component(s)) that is separate from a device (e.g., discrete component(s)) of the internal portion 20. In other words, the input shunt device 110 and the power management device 120 can be integrated into a standalone (e.g., single), discrete component (which can include a single or common semi-conductor substrate) defining the external portion 10. In some embodiments, the internal portion 20 of the input power protection device 100 can be integrated with at least a portion of a load 140 (e.g., can be on-board with the load 140). In some embodiments, any combination of elements (e.g., input shunt device 110, power management device 120, and output shunt device 130) of the input protection device 100 can be integrated into a standalone (e.g., single), discrete component (which can include a single or common semi-conductor substrate). For example, the input shunt device 110 can be a spark-gap device integrated with a power management device 120 that includes a junction field effect transistor (JFET) device (or a JFET-like device, a JFET-based device).
In some embodiments, the external portion 10 can be referred to as an off-board portion and the internal portion can be referred to as an on-board portion. In some embodiments, the input shunt device 110 included in the external portion 10 can be referred to as an external shunt device, and the output shunt device 130 included in the internal portion 20 can be referred to as an internal shunt device. The input shunt device 110 can be referred to as an input shunt device because the input shunt device 110 is coupled to (e.g., is disposed on) an input side of the power management device 120. The output shunt device 130 can be referred to as an output shunt device because the output shunt device 130 is coupled to (e.g., is disposed on) an output side of the power management device 120.