High speed, low power write current switching scheme for HDD preamplifier

An apparatus, comprising:

• a first differential pair of PNP BJTs having a first PNP BJT and a second PNP BJT;
• a first tail current source coupled into the emitter of the PNP BJTs of the first differential pair;
• a second differential pair of NPN BJTs having a first NPN BJT and a second NPN BJT;
• a second tail current source coupled into the emitters of the NPN BJTs of the second differential pair;
• wherein a collector of each of the PNP BJTs of the first differential pair are coupled to a corresponding collector the NPN BJTs of the second differential pair;
• a first shift up PNP BJT having an emitter coupled to the collector of a first PNP BJT of the first differential pair;
• a second shift up PNP BJT having an emitter coupled to the collector of the second PNP BJT of the first differential pair;
• a first shift down NPN BJT having an emitter coupled to the collector of the first PNP BJT of the second differential pair;
• a second shift up BJT having an emitter coupled to the collector of a second PNP BJT of the second differential pair;
• and
• a first and second amplifier coupled to the emitters of the a first shift up PNP BJT and the second shift up PNP BJT,
• a first static current source and a second static current source, an output of both of which are coupled to the base of the down shift transistor and the up shift transistor, respectively, and
• wherein the first static current source and the first tail current source share a node;
• and
• wherein the second static current source and the first tail current source share a node.

An apparatus, comprising:

• a first differential pair of PNP BJTs having a first PNP BJT and a second PNP BJT;
• a first tail current source coupled into the emitter of the PNP BJTs of the first differential pair;
• a second differential pair of NPN BJTs having a first NPN BJT and a second NPN BJT;
• a second tail current source coupled into the emitters of the NPN BJTs of the second differential pair;
• wherein a collector of each of the PNP BJTs of the first differential pair are coupled to a corresponding collector the NPN BJTs of the second differential pair;
• a first shift up PNP BJT having an emitter coupled to the collector of a first PNP BJT of the first differential pair;
• a second shift up PNP BJT having an emitter coupled to the collector of the second PNP BJT of the first differential pair;
• a first shift down NPN BJT having an emitter coupled to the collector of the first PNP BJT of the second differential pair;
• a second shift up BJT having an emitter coupled to the collector of a second PNP BJT of the second differential pair;
• and
• a first and second amplifier coupled to the emitters of the a first shift up PNP BJT and the second shift up PNP BJT,
• a first static current source and a second static current source, an output of both of which are coupled to the base of the down shift transistor and the up shift transistor, respectively, and
• wherein the first static current source and the first tail current source share a node;
• wherein the second static current source and the first tail current source share a node;
• and
• a diode coupled to the emitter of the first downshift BJT and the base of the first upshift BJT.