Low complexity high-speed multi-DAC system

Abstract

A multi-DAC system includes a plurality of DACs arranged in parallel for converting a digital signal to an analog signal, each DAC path having a different analog phase response. The system further includes a circuit for multiplying the digital signal input to at least some of the DACs by a multiplicand sufficient to shift a peak of a frequency response of the multi-DAC system to a non-DC frequency. For example, a series of +1 and/or −1 digital values can be used to multiply the digital signal so that the signal has the same number of bits pre and post multiplication. The multiplicand can include a constant series of +1 or −1 digital values, or a time-varying series of +1 and −1 digital values. In each case, the peak frequency response of the multi-DAC system can be shifted away from DC to a multiple of the sampling frequency of the DACs.

Dependencies are inferred from the claim text.