Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit

A voltage characteristic regulating method for regulating voltage characteristics of a plurality of latch circuits, each of the latch circuits comprising two nodes for retaining data, and a plurality of gate type transistors that are formed in a semiconductor substrate, the voltage characteristic regulating method comprising:

• applying a preset low voltage to power-supply voltage applied nodes of each of the latch circuits, each of the power-supply voltage applied nodes being applied a power-supply voltage thereto in normal operation of the plurality of latch circuits;
• and then
• applying a voltage that is higher than the power-supply voltage in the normal operation of the latch circuits and is able to nonvolatilely raise a threshold voltage of at least one of the gate type transistors of each of the latch circuits to each of the power-supply voltage applied nodes,
• the preset low voltage being lower than the power-supply voltage in the normal operation of the latch circuits and the preset low voltage being such that, in each of the latch circuits, each level of the two nodes is fixed and not able to be inverted.

A voltage characteristic regulating method for regulating voltage characteristics of a semiconductor device, the semiconductor device comprising:

• a first transistor being a p-conductivity gate type transistor and having a source connected with a power-supply voltage applied node that a power-supply voltage is applied thereto in the normal operation;
• a second transistor being a n-conductivity gate type transistor having a drain connected with a drain of the first transistor, a gate connected with a gate of the first transistor, and a source connected with a ground voltage applied node that is applied a ground voltage thereto in the normal operation;
• a third transistor being a p-conductivity gate type transistor having a source connected with the power-supply voltage applied node, a gate connected with a connecting node that is connected with the drain of the first transistor and the drain of the second transistor, and a drain connected with a connecting node that is connected with the gate of the first transistor and the gate of the second transistor;
• a fourth transistor being an n-conductivity gate type transistor having a drain connected with the drain of the third transistor, a gate connected with the gate of the third transistor and a source connected with the ground voltage applied node;
• a first access transistor being an n-conductivity gate type transistor having a gate connected with a word line that is applied a control voltage thereto in the normal operation, electrically connecting a connecting node that is connected with the drain of the first transistor and the drain of the second transistor with a first bit line that outputs data in turning on, and electrically disconnecting the connecting node that is connected with the drain of the first transistor and the drain of the second transistor with the first bit line in turning off;
• and
• a second access transistor being an n-conductivity gate type transistor having a gate connected with the word line, electrically connecting a connecting node that is connected with the drain of the third transistor and the drain of the fourth transistor with the second bit line that outputs data and differs from the first bit line in turning on, and electrically disconnecting the connecting node that is connected with the drain of the third transistor and the drain of the fourth transistor with the second bit line in turning off,
• each of the first transistor, the second transistor, the third transistor, the fourth transistor, the first access transistor, and the second access transistor being formed in a semiconductor substrate respectively,
• the voltage characteristic regulating method comprising:
• applying a preset low voltage to the power-supply voltage applied node in the normal operation of the semiconductor device, the preset low voltage being lower than the power-supply voltage in the normal operation of the semiconductor device and the preset low voltage being such that each level of the two nodes is fixed and not able to be inverted;
• applying a voltage that is higher than the power-supply voltage in the normal operation of the semiconductor device and is able to nonvolatilely raise a threshold voltage of at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the first access transistor, and the second access transistor to the power-supply voltage applied node;
• applying a normal operation substrate voltage applied in the normal operation of the semiconductor device to the semiconductor substrate;
• and then
• adjusting at least one of the preset low voltage and the normal operation substrate voltage so that an adjusted voltage difference between the power-supply voltage applied node and the semiconductor substrate is equal to or higher than a preset voltage difference that is larger than an unadjusted voltage difference between the power-supply voltage applied node and the semiconductor substrate in the normal operation of the semiconductor device.