Generating high-frequency, non-overlapping clocks
AssigneeBroadcom Corporation
InventorsDavid Murphy, Hooman Darabi, Hao Xu
Life of this patent
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Abstract
A method for generation of high frequency, non-overlapping clocks may include receiving input clock signals at a clock input node of a circuit. Multiple feedback signals may be received at a number of input feedback nodes of the circuit. At a startup node, a startup signal of the circuit may be received, and, in response to receiving the startup signal, an output clock may be generated at a predefined portion of at least one of the received input clock signals. A stable high frequency output clock may be generated at an output stage by utilizing the feedback signals received by the input feedback nodes.
Claims21
A circuit for high frequency, non-overlapping clocks generation, the circuit comprising:
- a clock input node disposed to receive input clock signals;
- a plurality of input feedback nodes disposed to receive a plurality of feedback signals;
- a startup node disposed to receive a startup signal and, in response to receiving the startup signal, generate an output clock at a predefined portion of at least one of the received input clock signals;
- and
- an output stage configured to provide the output clock, wherein,
- the plurality of feedback signals received by the plurality of input feedback nodes are utilized to provide a stable high frequency output clock.
A method for generation of high frequency, non-overlapping clocks, the method comprising:
- receiving input clock signals at a clock input node of a circuit;
- receiving a plurality of feedback signals at a plurality of input feedback nodes of the circuit;
- receiving a startup signal at a startup node of the circuit and, in response to receiving the startup signal, generating an output clock at a predefined portion of at least one of the received input clock signals;
- and
- providing, at an output node of the circuit, a stable high frequency output clock by utilizing the feedback signals received by the plurality of input feedback nodes.
A passive mixer circuit comprising:
- a radio frequency (RF) input node disposed to receive an RF signal;
- a multiphase local oscillator (LO) configured to generate a plurality of non-overlapping clock signal;
- and
- a plurality of multipliers, each of the plurality of multipliers configured to multiply the RF signal with one of the plurality of non-overlapping clock signals, wherein:
- a) the plurality of non-overlapping clock signals comprise M non-overlapping clock signals generated by register cells of an M-register clock generator circuit,
- b) each register cell of the M-register clock generator circuit is configured to generate a clock of the plurality of non-overlapping clocks, and comprises:
- a clock input node disposed to receive an input clock signal;
- a plurality of input feedback nodes disposed to receive a plurality of feedback signals;
- a startup node disposed to receive a startup signal and, in response to receiving the startup signal, generate a clock signal of at a predefined portion of the received input clock signal;
- and
- an output stage configured to provide a clock signal of the plurality of non-overlapping clock signals, wherein,
- the feedback signals received by the plurality of input feedback nodes are utilized to provide a stable high frequency clock signal.
Dependencies are inferred from the claim text.