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US 8,618,856 B1Granted
Shadow latch
AssigneeApplied Micro Circuits Corporation
InventorsAlfred Yeung, Hamid Partovi, John Ngai, Ronen Cohen
Life of this patent
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Abstract
A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.
Claims17
A latch device comprising:
- a driver comprising
- an input to accept a binary driver input signal,
- an input to accept a clock signal,
- an input to accept a shadow-Q signal, and
- an output to supply a binary Q signal equal to an inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal,
- a first clocked inverter circuit having an input to accept the driver input signal, an input to accept the clock signal, and an output to supply the Q signal, and
- a second clocked inverter circuit having an input to accept the shadow-Q signal, an input to accept the clock signal, and an output to supply the Q signal;
- and
- a shadow latch having an input to accept the driver input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal equal to an inverted Q signal, in response to the driver input signal and clock signal.
6 more elements
A method for stabilizing an unbuffered latch, comprising:
- providing a single gate delay driver;
- supplying a binary driver input signal, with a first polarity, to an input of the driver;
- in response to a first clock signal, transferring a second polarity of the driver input signal to a driver (Q) output, with no more than one gate delay;
- regardless of spurious signals received at the driver output, maintaining the second polarity at the driver (Q) output until a second clock signal is received, subsequent to the first clock signal, wherein maintaining the second polarity of the driver (Q) output comprises maintaining the second polarity in response to the shadow-Q signal;
- and
- generating a shadow-Q signal in response to the first clock signal, wherein generating the shadow-Q signal comprises generating the shadow-Q signal decoupled from the driver (Q) output.
3 more elements
A single gate delay latch comprising:
- a first circuit having an interface to accept an input signal with a first binary state, an interface to accept a binary clock signal, and an interface to supply a Q signal with a second binary state opposite to the first binary state and delayed by a single gate, the first circuit maintaining the Q signal second binary state during a first clock polarity;
- a second circuit having an interface to accept a shadow-Q signal, and interface to accept the clock signal, and an interface to supply the Q signal, the second circuit maintaining the Q signal second binary state during a second clock polarity, opposite to the first polarity, wherein the second circuit is a clocked inverter;
- and,
- a shadow circuit having an interface to accept the input signal with the first binary state, an interface to accept the clock signal and an interface to supply the shadow-Q signal.
1 more element
A single gate delay latch comprising:
- a first circuit having an interface to accept an input signal with a first binary state, an interface to accept a binary clock signal, and an interface to supply a Q signal with a second binary state opposite to the first binary state and delayed by a single gate, the first circuit maintaining the Q signal second binary state during a first clock polarity;
- a second circuit having an interface to accept a shadow-Q signal, and interface to accept the clock signal, and an interface to supply the Q signal, the second circuit maintaining the Q signal second binary state during a second clock polarity, opposite to the first polarity;
- and,
- a shadow circuit having an interface to accept the input signal with the first binary state, an interface to accept the clock signal, and an interface to supply the shadow-Q signal, the shadow circuit comprises:
- a third circuit having an interface to accept the input signal with the first binary state, an interface to accept the clock signal, and an interface to supply a D1 signal with the second binary state, delayed by a single gate, the third circuit maintaining the D1 signal second binary state during the first clock polarity;
- an inverter having an input to accept the D1 signal and an output to supply the shadow-Q signal;
- and,
- a fourth circuit having an interface to accept the shadow-Q signal, and interface to accept the clock signal, and an interface to supply the D1 signal, the fourth circuit maintaining the D1 signal second binary state during the second clock polarity.
5 more elements
Dependencies are inferred from the claim text.