Adaptive clock switching to capture asynchronous data within a phase-to-digital converter

An apparatus comprising:

• a Phase-to-Digital Converter (PDC) portion that receives a reference signal and a feedback signal and generates therefrom a stream of multi-bit digital values, wherein each of the multi-bit digital values is indicative of a time difference between an edge of the reference signal and a corresponding edge of the feedback signal;
• a PDC decoder portion that includes a plurality of sequential logic elements, wherein the PDC portion supplies the stream of multi-bit digital values onto data inputs of the plurality of sequential logic elements of the PDC decoder portion;
• and
• an adaptive clock signal adjusting circuit that supplies a clock signal to the plurality of sequential logic elements and adjusts timing of the clock signal that clocks the plurality of sequential logic elements as a function of the time difference between the reference signal and the feedback signal, wherein the PDC portion, the PDC decoder portion and the adaptive clock signal adjusting circuit are parts of a Phase-to-Digital Converter (PDC).

An apparatus comprising:

• a Phase-to-Digital Converter (PDC) portion that receives a reference signal and a feedback signal and generates therefrom a stream of multi-bit digital values;
• a Phase-to-Digital Converter (PDC) decoder portion, wherein the PDC decoder portion includes a plurality of sequential logic elements that receives the stream of multi-bit digital values from the PDC portion;
• and
• means for adjusting timing of a clock signal that clocks the plurality of sequential logic elements as a function of a difference between the reference signal and the feedback signal.