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US 8,618,853 B2Granted
Device including a clock generation circuit and a method of generating a clock signal
OwnerYoshio Mizukane, Hiroki Fujisawainventors
Life of this patent
Estimating the term…
Abstract
A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
Claims20
A device comprising;
- a plurality of flip-flop circuits each of which includes input, output and clock nodes, the flip-flop circuits being connected such that an output node of a preceding one of the flip-flop circuits is connected to an input node of a succeeding one of the flip-flop circuits, the clock nodes of flip-flop circuits being connected in common to a clock input node;
- a circuit node supplied with a clock signal;
- a gate circuit supplied between the circuit node and the clock input node and configured to be controlled in open and close states thereof in response to a first signal derived from the output node of a first one of the flip-flop circuits;
- and
- a first circuit configured to receive a second signal from the output node of a second one of the flip-flop circuits, that is prior to the first one of flip-flop circuits, and to perform an operation in response to the second signal.
2 more elements
A device comprising;
- a plurality of flip-flop circuits each of which includes input, output and clock nodes, the flip-flop circuits being connected such that an output node of a preceding one of the flip-flop circuits is connected to an input node of a succeeding one of the flip-flop circuits, the clock terminals of each of the flip-flop circuits receiving a clock signal, a first one of the flip-flop circuits producing a first signal, that takes one of first and second logic levels, at the output node thereof, a second one of the flip-flop circuits, that is prior to the first one of the flip-flop circuits, producing a second signal at the output node thereof;
- a first circuit receiving the first signal and configured to supply the clock signal to the flip-flop circuits when the first signal takes the first logic level and to stop supplying the clock signal to the flip-flop circuits when the first signal takes the second logic level;
- and
- a second circuit configured to perform an operation in response to the second signal.
1 more element
Dependencies are inferred from the claim text.