Differential PVT/timing-skew-tolerant self-correcting circuits
AssigneeQUALCOMM Incorporated
InventorChang Ki Kwon
Life of this patent
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Abstract
Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor.
Claims36
A circuit, comprising:
- a first inverter;
- a first non-inverting buffer, wherein the first inverter and the first non-inverting buffer have a first common input configured to receive a signal to be buffered by the first non-inverting buffer;
- a second inverter;
- a second non-inverting buffer, wherein the second inverter and the second non-inverting buffer have a second common input,
- wherein the output of the first inverter is coupled to the output of the second non-inverting buffer,
- wherein the output of the second inverter is coupled to the output of the first non-inverting buffer;
- and
- a bias network having:
- a respective positive bias circuit and a respective negative bias circuit coupled to each inverter;
- and
- a respective positive bias circuit and a respective negative bias circuit coupled to each non-inverting buffer.
A method for improving output signals in a complementary logic circuit, comprising:
- biasing an n-type transistor in the complementary logic circuit with a first variable power supply;
- and
- biasing a p-type transistor in the complementary logic circuit with a second variable power supply to mitigate a difference in the switching times of the p-type transistor and the n-type transistor,
- wherein the second variable power supply provides a voltage different from that of the first variable power supply.
A circuit, comprising:
- means for biasing an n-type transistor in the complementary logic circuit with a first variable power supply;
- and
- means for biasing a p-type transistor in the complementary logic circuit with a second variable power supply to mitigate a difference in the switching times of the p-type transistor and the n-type transistor,
- wherein the second variable power supply provides a voltage different from that of the first variable power supply.
A non-transitory computer-readable medium, comprising instructions stored thereon that, if executed by a lithographic device, cause the lithographic device to fabricate at least a part of an integrated circuit, comprising:
- a first inverter;
- a first non-inverting buffer, wherein the first inverter and the first non-inverting buffer have a first common input configured to receive a signal to be buffered by the first non-inverting buffer;
- a second inverter;
- a second non-inverting buffer, wherein the second inverter and the second non-inverting buffer have a second common input,
- wherein the output of the first inverter is coupled to the output of the second non-inverting buffer,
- wherein the output of the second inverter is coupled to the output of the first non-inverting buffer;
- and
- a bias network having:
- a respective positive bias circuit and a respective negative bias circuit coupled to each inverter;
- and
- a respective positive bias circuit and a respective negative bias circuit coupled to each non-inverting buffer.
Dependencies are inferred from the claim text.