Method for reducing spurious for a clock distribution system
AssigneeHittite Microwave Corporation
InventorMark Cloutier
Life of this patent
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Abstract
A method for reducing spurious for a clock distribution system, the method including a) providing a system controller, b) providing clock distribution system, c) inputting characteristics of the clock distribution system in advance of operation thereof, d) calculating an expected level of the integer boundary spurious as a function of a fractional offset value, e) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region, and f) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution, and g) repeating steps d) through f) as needed.
Claims20
A method for reducing spurious for a clock distribution system, the method comprising:
- a) providing a system controller;
- b) providing a clock distribution system including:
- a master clock subsystem responsive to an external reference signal configured to generate a master clock signal and one or more intermediate clock signals each at a sub-multiple of the master clock signal, and
- one or more fractional synthesizers each responsive to one of the one or more intermediate clock signals and each configured to generate an output signal at a desired frequency from a wide range of possible output frequencies based on a command from the system controller;
- c) inputting characteristics of the clock distribution system in advance of operation thereof;
- d) calculating an expected level of the integer boundary spurious as a function of fractional offset value to select a preferred region of operation;
- e) providing a desired frequency of the output signal of operation;
- f) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region;
- and
- g) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution;
- and
- h) repeating steps e) through g) as needed.
A method for reducing spurious for a clock distribution system, the method comprising:
- a) providing a system controller;
- b) providing a clock distribution system including:
- a master clock subsystem responsive to an external reference signal configured to generate a master clock signal and one or more intermediate clock signals each at a sub-multiple of the master clock signal, and
- one or more fractional synthesizers each responsive to one of the one or more intermediate clock signals and each configured to generate an output signal at a desired frequency from a wide range of possible output frequencies based on a command from the system controller;
- c) inputting characteristics of the clock distribution system in advance of operation thereof;
- d) providing a desired operating frequency of the output signal;
- e) calculating possible candidate frequencies of the one or more intermediate clock signals;
- f) calculating possible candidate frequencies of a phase detector of each of said one or more fractional synthesizers;
- g) calculating the frequency offset from the nearest integer boundary (IB) of each of said candidate frequencies;
- h) calculating integer and fractional parts of the output signal for each of the candidate frequencies;
- i) rejecting any candidate frequencies outside of an acceptable range of said characteristics of the clock distribution system;
- j) calculating an expected level of the integer boundary spurious for each remaining candidate frequency;
- k) if any of said candidate frequencies are an integer boundary solution, select that candidate frequency solution, otherwise, select a candidate frequency solution that generates the lowest expected level of the integer boundary spurious;
- l) programming the master clock subsystem and the one or more fractional synthesizers with the candidate frequency solution;
- and
- m) repeating steps d) through l) as needed.
Dependencies are inferred from the claim text.