Balanced single-ended impedance control

A method of generating a balanced single-ended impedance, the method comprising:

• generating a first rail voltage at a first control path;
• generating a second rail voltage at a second control path;
• controlling a first gate control voltage of a first transistor based on the first rail voltage, the first transistor coupled to a first output terminal, wherein the first control path is coupled to a third transistor and wherein device characteristics of the third transistor substantially match device characteristics of the first transistor;
• controlling a second gate control voltage of a second transistor based on the second rail voltage, the second transistor coupled to a second output terminal, wherein the second control path is coupled to a fourth transistor and wherein device characteristics of the fourth transistor substantially match device characteristics of the second transistor;
• providing a gate control signal to the first transistor;
• and
• providing the gate control signal to the second transistor.

An apparatus comprising:

• means for generating a first rail voltage;
• means for generating a second rail voltage;
• means for controlling a first gate control voltage of a first transistor based on the first rail voltage, the first transistor coupled to a first output terminal, wherein the means for generating the first rail voltage includes a third transistor and wherein device characteristics of the third transistor substantially match device characteristics of the first transistor;
• and
• means for controlling a second gate control voltage of a second transistor based on the second rail voltage, the second transistor coupled to a second output terminal, wherein the means for generating the second rail voltage includes a fourth transistor and wherein device characteristics of the fourth transistor substantially match device characteristics of the second transistor;
• and
• means for providing a gate control signal to the first transistor and to the second transistor.

A method comprising:

• a step for generating a first rail voltage at a first control path;
• a step for generating a second rail voltage at a second control path;
• a step for controlling a first gate control voltage of a first transistor based on the first rail voltage, the first transistor coupled to a first output terminal, wherein the first control path is coupled to a third transistor and wherein device characteristics of the third transistor substantially match device characteristics of the first transistor;
• a step for controlling a second gate control voltage of a second transistor based on the second rail voltage, the second transistor coupled to a second output terminal, wherein the second control path is coupled to a fourth transistor and wherein device characteristics of the fourth transistor substantially match device characteristics of the second transistor;
• a step for providing a gate control signal to the first transistor;
• and
• a step for providing the gate control signal to the second transistor.