US 8,618,667 B2Granted

Semiconductor device and method of manufacturing the same

AssigneeHitachi, Ltd.

InventorsKenichi Takeda, Mayu Aoki, Kazuyuki Hozawa

Life of this patent

Estimating the term…

Loading patent…

Abstract

A bump electrode, a dummy bump, and a heat-resistant polymer film, whose upper-surface heights are uniformed, are formed on each of a first silicon substrate and a second silicon substrate, and then, the first silicon substrate and the second silicon substrate are bonded to each other so that the bump electrodes formed on the respective substrates are electrically connected to each other. At this time, the dummy bump is arranged so as to be bonded to the heat-resistant polymer film on the silicon substrate opposed thereto, so that a semiconductor device having both of good electrical connection between the bump electrodes and bump protection performance obtained by a polymer film with high heat resistance and without voids can be achieved.

A semiconductor device comprising:

a first substrate on whose one surface a first electrode and a first insulating film are formed;
and a second substrate on whose one surface a second electrode and a second insulating film are formed, and the first substrate and the second substrate being layered and being electrically connected to each other by bonding the one surface of the first substrate and the one surface of the second substrate, wherein
the first electrode is formed in a first region of the first insulating film, a first dummy bump made of the same material as a material of the first electrode is formed in a second region of the first insulating film, the second electrode is formed in a first region of the second insulating film, and a second dummy bump made of the same material as a material of the second electrode is formed in a second region of the second insulating film,
in a direction vertical to the one surface of the first substrate, a distance from the one surface of the first substrate to an upper surface of the first electrode, a distance from the one surface of the first substrate to an upper surface of the first dummy bump, and a distance from the one surface of the first substrate to an upper surface of the first insulating film are equal to each other,
in a direction vertical to the one surface of the second substrate, a distance from the one surface of the second substrate to an upper surface of the second electrode, a distance from the one surface of the second substrate to an upper surface of the second dummy bump, and a distance from the one surface of the second substrate to an upper surface of the second insulating film are equal to each other,
the first dummy bump is in contact with the second insulating film, and the second dummy bump is in contact with the first insulating film, and
the first insulating film and the second insulating film contain at least one of polyimide, polybenzoxazole, and benzocyclobutene.

4 more elements

Facts

Application

13/443,869Filed 10 Apr 2012

Priority

JP 2011-08706111 Apr 2011

Published

US 2012/0256311 A111 Oct 2012

Granted

31 Dec 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification29 codes

H10W 90/00
Package configurations
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 72/01238
Using blanket deposition: in gaseous form, e.g. by CVD or PVD
H10W 72/01251
Of bump connectors, dummy bumps or thermal bumps: changing the shapes of bumps

Abstract

Claims7