Back to results
US 8,618,665 B2Granted
Pattern layout in semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsGo Shikata, Fumiharu Nakajima, Toshiaki Edahiro
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below.
Claims13
A semiconductor device having a pattern layout comprising:
- a first power supply line which extends in one direction and to which a first voltage is supplied;
- second and third power supply lines which extend in the one direction and are arranged to sandwich the first power supply line therebetween and to which a second voltage is supplied;
- a first signal line which is arranged between the first power supply line and the second power supply line and to which data read from memory cells is transmitted;
- a second signal line which is arranged between the first power supply line and the third power supply line and to which data read from the memory cells is transmitted;
- a first contact pad which is connected to the second power supply line and electrically connected to an upper interconnect line arranged on the second power supply line;
- and
- a second contact pad which is connected to the third power supply line and electrically connected to an upper interconnect line arranged on the third power supply line.
4 more elements
A semiconductor device having a pattern layout comprising:
- a memory cell array having memory cells;
- a sense amplifier which is arranged at one end of the memory cell array and reads data stored in the memory cells,
- a first interconnect pattern in which lines and spaces are alternately aligned in a first direction with a predetermined pitch;
- and
- a contact pad which is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch,
- wherein the first interconnect pattern and the contact pad are arranged in a region where the sense amplifier is formed,
- an interval between the lines in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below,
- a planar shape of the contact pad is an H-like shape,
- the first interconnect pattern comprises:
- a first power supply line which extends in a second direction and to which a first voltage is supplied;
- second and third power supply lines which extend in the second direction and are arranged to sandwich the first power supply line therebetween and to which a second voltage is supplied;
- a first signal line which is arranged between the first power supply line and the second power supply line and to which data read from the memory cells is transmitted;
- and
- a second signal line which is arranged between the first power supply line and the third power supply line and to which data read from the memory cells is transmitted;
- and
- the contact pad comprises:
- a first contact pad which is connected to the second power supply line and electrically connected to an upper interconnect line arranged on the second power supply line;
- and
- a second contact pad which is connected to the third power supply line and electrically connected to an upper interconnect line arranged on the third power supply line.
16 more elements
A semiconductor device having a pattern layout comprising:
- a memory cell array having memory cells;
- a sense amplifier which is arranged at one end of the memory cell array and reads data stored in the memory cells,
- a first interconnect pattern in which lines and spaces are alternately aligned in a first direction with a predetermined pitch;
- and
- a contact pad which is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch,
- wherein the first interconnect pattern and the contact pad are arranged in a region where the sense amplifier is formed,
- an interval between the lines in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below,
- a planar shape of the contact pad is a rectangular shape,
- the first interconnect pattern comprises:
- a first power supply line which extends in a second direction and to which a first voltage is supplied;
- second and third power supply lines which extend in the second direction and are arranged to sandwich the first power supply line therebetween and to which a second voltage is supplied;
- a first signal line which is arranged between the first power supply line and the second power supply line and to which data read from the memory cells is transmitted;
- and
- a second signal line which is arranged between the first power supply line and the third power supply line and to which data read from the memory cells is transmitted;
- and
- the contact pad comprises:
- a first contact pad which is connected to the second power supply line and electrically connected to an upper interconnect line arranged on the second power supply line;
- and
- a second contact pad which is connected to the third power supply line and electrically connected to an upper interconnect line arranged on the third power supply line.
16 more elements
Dependencies are inferred from the claim text.