Die having coefficient of thermal expansion graded layer
AssigneeTexas Instruments Incorporated
InventorsBrian K. Kirkpatrick, Rajesh Tiwari
Life of this patent
Estimating the term…
Loading patent…
AssigneeTexas Instruments Incorporated
InventorsBrian K. Kirkpatrick, Rajesh Tiwari
Estimating the term…
A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.
A semiconductor die, comprising:
A semiconductor die, comprising:
A method of fabricating a semiconductor die including circuit elements configured to provide a circuit function, comprising:
Dependencies are inferred from the claim text.