Buried TSVs used for decaps

A packaged semiconductor structure comprising:

• a packaging substrate;
• an interposer disposed on the packaging substrate;
• at least a first IC chip mounted on and electrically coupled to the interposer, the interposer comprising:
• a substrate comprising a silicon material, a bottom surface of the substrate defining a PCB mounting surface;
• an interconnect layer disposed on the substrate, the interconnect layer comprising conductive and dielectric layers patterned to form a plurality of top wires, a top surface of the interconnect layer defining a chip mounting surface;
• a plurality of through-vias formed through the substrate in an isolated region of the substrate, at least one of the plurality of conductive vias electrically coupled to at least one of the top wires;
• a plurality of blind-vias formed through the substrate in a dense region of the substrate, the through-vias and blind vias formed during a common etching step, at least one blind-via comprising:
• (a) a dielectric material lining the blind-vias;
• and
• (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.

A method for forming a structure having decoupling capacitors, the method comprising:

• performing an etching process to form vias in a plurality of regions of a silicon substrate, at least a first region having a via density per unit area greater than a second region;
• lining the vias with a dielectric material;
• depositing a conductive material to fill the lined vias;
• and
• thinning back the substrate to form conductive vias extending from a top of the substrate to a bottom of the substrate in the second region, and to form decaps in blind-vias in the first region.