Compliant printed circuit semiconductor package
AssigneeHsio Technologies, LLC
InventorJames Rathburn
Life of this patent
Estimating the term…
Abstract
A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.
Claims19
A package for a semiconductor device having electrical terminals, the package comprising:
- a substrate including at least one semiconductor device;
- a first dielectric layer selectively printed on at least a portion of the semiconductor device comprising first recesses aligned with a plurality of the electrical terminals;
- a conductive material printed in the first recesses forming contact members on the semiconductor device;
- a second dielectric layer selectively printed on at least a portion of the first dielectric layer comprising second recesses aligned with a plurality of the first recesses;
- a conductive material printed in at least a portion of the second recesses comprising a circuit geometry;
- a third dielectric layer selectively printed on at least a portion of the second dielectric layer comprising third recesses aligned with a portion of the circuit geometry;
- a conductive material printed in the third recesses comprising a plurality of exposed terminals that are offset from, and electrically coupled to the electric terminals on the semiconductor device by the circuit geometry;
- and
- a compliant material deposited in recesses in one or more of the first, second or third dielectric layers adjacent to a plurality of the exposed terminals to permit the exposed terminals to move within the dielectric layers relative to the substrate.
A package for a semiconductor device having electrical terminals, the package comprising:
- at least one first dielectric layer selectively printed directly on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals;
- a conductive material located in the first recesses forming contact members that are electrically coupled to the electric terminals on the semiconductor device;
- at least one second dielectric layer selectively printed on at least one first dielectric layer to create a plurality of second recesses corresponding to a target circuit geometry;
- a conductive material located in at least a portion of the second recesses comprising circuit geometry located on the semiconductor device, the circuit geometry comprising a plurality of exposed terminals that are offset from, and electrically coupled to the contact members by the circuit geometry;
- and
- a compliant material deposited in additional recesses in one or more of the first or second dielectric layers adjacent to a plurality of the exposed terminals, wherein the complaint material permits the exposed terminals to move within the dielectric layers relative to the substrate.
Dependencies are inferred from the claim text.