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US 8,618,648 B1Granted
Methods for flip chip stacking
AssigneeXilinx, Inc.
InventorsWoon-Seong Kwon, Suresh Ramalingam
Life of this patent
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Abstract
A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.
Claims18
A method for flip chip stacking, comprising:
- forming a cavity wafer by forming a plurality of cavities within an electrostatic (ESC) chuck wafer and forming a bonding layer on a surface of the ESC chuck wafer;
- placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated on the bonding layer;
- applying an electrostatic bias to the bonding layer to bond the TSV interposer to the cavity wafer;
- placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit;
- and
- removing the stacked interposer unit from the cavity wafer.
3 more elements
A system for flip chip stacking, comprising:
- an electrostatic (ESC) chuck wafer having a plurality of cavities in the ESC chuck wafer;
- and
- a bonding layer on a surface of the ESC chuck wafer;
- and
- a through silicon via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer, wherein the solder bumps are situated in the plurality of cavities;
- and
- an integrated circuit (IC) die on another surface of the TSV interposer, wherein the IC die and the TSV interposer with the solder bumps form a stacked interposer unit;
- wherein the bonding layer has one or more surfaces above which the through-silicon-via interposer with the solder bumps is situated;
- wherein the cavities have respective dimensions and positions for allowing the cavities to receive the solder bumps of the TSV interposer;
- wherein the ESC chuck wafer is bonded to the TSV interposer with the solder bumps in response to the bonding layer receiving an electrostatic charge;
- and
- wherein the TSV interposer with the solder bumps is removable from the cavities in response to a removal of the electrostatic charge applied to the bonding layer.
9 more elements
Dependencies are inferred from the claim text.