Layered chip package and method of manufacturing same

A composite layered chip package comprising a plurality of subpackages stacked, every vertically adjacent two of the subpackages being electrically connected to each other,

• each of the plurality of subpackages including a main body having a top surface and a bottom surface, the main body including:
• a main part having a top surface and a bottom surface;
• a plurality of first terminals disposed on the top surface of the main part;
• and
• a plurality of second terminals disposed on the bottom surface of the main part, wherein:
• the main part includes a first layer portion and a second layer portion stacked, and a plurality of through electrodes that each penetrate the first and second layer portions;
• the plurality of through electrodes are electrically connected to the plurality of first terminals and the plurality of second terminals;
• each of the first and second layer portions includes a semiconductor chip and a plurality of surface electrodes, the semiconductor chip of each of the first and second layer portions having a first surface and a second surface opposite to the first surface, the plurality of surface electrodes of each of the first and second layer portions being disposed on a side of the semiconductor chip opposite to the second surface of the semiconductor chip;
• the first layer portion and the second layer portion are bonded directly to each other such that the second surface of the semiconductor chip of the first layer portion and the second surface of the semiconductor chip of the second layer portion face each other;
• the plurality of surface electrodes of the first layer portion have a layout that is the same as a layout of the plurality of surface electrodes of the second layer portion;
• the plurality of surface electrodes of each of the first and second layer portions include a plurality of first terminal component parts and a plurality of second terminal component parts;
• the plurality of first terminal component parts of the plurality of surface electrodes of the first layer portion are used to form the plurality of first terminals whereas the plurality of second terminal component parts of the plurality of surface electrodes of the first layer portion are not used to form the plurality of first terminals;
• the plurality of second terminal component parts of the plurality of surface electrodes of the second layer portion are used to form the plurality of second terminals, whereas the plurality of first terminal component parts of the plurality of surface electrodes of the second layer portion are not used to form the plurality of second terminals;
• and
• for any vertically adjacent two of the subpackages, the plurality of second terminals of the upper one of the subpackages are electrically connected to the plurality of first terminals of the lower one.