US 8,618,645 B2Granted

Package process and package structure

AssigneeAdvanced Semiconductor Engineering, Inc.

InventorsChi-Chih Shen, Jen-Chuan Chen, Tommy Pan

Life of this patent

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Abstract

A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

Claims10

Dependent claims

A package structure, comprising:

a circuit substrate;
a first semiconductor device formed on the circuit substrate, wherein the first semiconductor device is a functional device and has a plurality of through-silicon via structures;
a first molding compound enclosing a first sidewall of the first semiconductor device;
a second semiconductor device formed on the first semiconductor device and a first portion of the first molding compound, wherein a dimension of the second semiconductor device is larger than a dimension of the first semiconductor device;
a second molding compound at least covering a second sidewall of the second semiconductor device and the rest portion of the top surface of the first molding compound, wherein the first molding compound and the second molding compound are individually formed;
a plurality of conductive bumps directly attached a bottom surface of the first semiconductor device and a top surface of the circuit substrate;
and
an encapsulant formed on the circuit substrate to cover at least a third sidewall of the first molding compound and a fourth sidewall of the second molding compound.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/711,870Filed 24 Feb 2010
Priority: TW 98133269 A30 Sep 2009
Published: US 2011/0074004 A131 Mar 2011
Granted: 31 Dec 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification32 codes

H10W 74/121
The semiconductor body being completely enclosed: by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 74/014
Manufacture or treatment: using batch processing