Method of shielding through silicon vias in a passive interposer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsiang-Tai Lu, Chih-Hsien Lin, Meng-Lin Chung
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Abstract
A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.
Claims20
A passive interposer apparatus with a shielded through silicon via (TSV) configuration, the apparatus comprising:
- a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped and extends substantially across an entirety of the p-doped substrate;
- an interlayer dielectric layer (ILD) disposed over the upper portion of the p-doped substrate;
- a plurality of through silicon vias (TSVs) formed through the ILD and the p-doped substrate, wherein the plurality of TSVs electrically couple respective first metal contact pads above the ILD to a first set of bump structures below the p-doped substrate;
- and
- a plurality of shielding lines electrically coupling respective second metal contact pads to the upper portion of the p-doped substrate, wherein the shielding lines are disposed between adjacent TSVs of the plurality of TSVs.
An integrated circuit device configured to reduce signal coupling between through silicon vias (TSVs), the device comprising:
- a first semiconductor wafer having a substrate portion and an active circuitry portion, wherein the active circuitry portion is electrically coupled to bump structures configured for bonding to a passive interposer;
- and
- a passive interposer without active circuitry, wherein the interposer includes
- a p-doped substrate, wherein the p-doped substrate has an upper portion and a lower portion that are each heavily doped, and has a central portion that is moderately doped;
- an interlayer dielectric (ILD) above the upper portion of the p-doped substrate;
- a plurality of through silicon vias (TSVs) formed through the ILD and the p-doped substrate, where the plurality of TSVs are configured to electrically couple an interconnect structure above the ILD and a bump structure below the p-doped substrate;
- a plurality of shielding lines configured to electrically couple the interconnect structure above the ILD and the heavily doped upper portion of the p-doped substrate;
- and
- at least one TSV of the plurality of TSVs and at least one shielding line of the plurality of shielding lines connect to one or more interconnect layers formed above the first and second metal contact pads.
An interposer having a shielded through silicon via (TSV) configuration, the interposer comprising:
- a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped;
- an interlayer dielectric layer (ILD) disposed over the upper portion of the p-doped substrate;
- a first TSV formed through the ILD and the p-doped substrate, the first TSV coupled to a first metal contact pad above the ILD and a first bump structure below the p-doped substrate;
- a second TSV formed through the ILD and the p-doped substrate, the second TSV coupled to a second metal contact pad above the ILD and a second bump structure below the p-doped substrate;
- a shielding line disposed between the first TSV and the second TSV, the shielding line coupled to a third metal contact pad above the ILD and a top surface of the upper portion of the p-doped substrate;
- and
- the first TSV and the shielding line are connected to a first interconnect pad.
Dependencies are inferred from the claim text.