Semiconductor-on-insulator apparatus, device and system with buried decoupling capacitors
AssigneeMicron Technology, Inc.
InventorBadih El-Kareh
Life of this patent
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Abstract
A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.
Claims24
An apparatus, comprising:
- a semiconductor-on-insulator substrate including a buried insulator region and top semiconductor region on the buried insulator region, the top semiconductor region including a doped region and a non-doped region;
- a first capacitor plate of a capacitor including the doped region in the top semiconductor region in the semiconductor-on-insulator substrate;
- a dielectric material on the first capacitor plate;
- and
- a second capacitor plate of the capacitor on the dielectric material, wherein the second capacitor plate includes a metal.
An apparatus, comprising:
- a silicon-on-insulator substrate including a buried insulator region and top silicon region on the buried insulator region, the top silicon region including a doped region and a non-doped region;
- a first capacitor plate of a capacitor including the doped region in the top silicon region in the silicon-on-insulator substrate;
- a dielectric material on the first capacitor plate;
- and
- a second capacitor plate of the capacitor on the dielectric material, wherein the second capacitor plate includes a silicon film, and wherein the second capacitor plate includes a source/drain region within the silicon film.
A device, comprising:
- at least one semiconductor die, the die including at least one buried decoupling capacitor, the capacitor comprising:
- a semiconductor-on-insulator substrate including a buried insulator region and top semiconductor region on the buried insulator region, the top semiconductor region including a doped region and a non-doped region;
- a first capacitor plate including the doped region in the top semiconductor region in the semiconductor-on-insulator substrate;
- a dielectric material on the first capacitor plate;
- and
- a second capacitor plate on the dielectric material, wherein the second capacitor plate includes a source/drain region.
A system, comprising:
- a processor;
- a memory system coupled to the processor, wherein the memory system is on a substrate and comprises a plurality of devices;
- and
- at least one buried decoupling capacitor in the substrate, the capacitor comprising:
- a semiconductor-on-insulator substrate including a buried insulator region and top semiconductor region on the buried insulator region, the top semiconductor region including a doped region and a non-doped region;
- a first capacitor plate including the doped region in the top semiconductor region in the semiconductor-on-insulator substrate;
- a dielectric material on the first capacitor plate;
- and
- a second capacitor plate on the dielectric material, wherein the second capacitor plate includes a source/drain region.
Dependencies are inferred from the claim text.