Shielded level shift transistor
AssigneeFairchild Semiconductor Corporation
InventorsSunglyong Kim, Jongjib Kim
Life of this patent
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Abstract
A semiconductor device can include a transistor and an isolation region. The transistor is formed in a semiconductor substrate having a first conductivity type. The transistor includes a drift region extending from a drain region toward a source region and having a second conductivity type. The drift region includes a first resurf region near a working top surface and having the first conductivity type. The high voltage isolation island region includes a first well region laterally offset from the drift region. The first well region has the second conductivity type. An isolation region is located laterally between the drain region and the first well region. The isolation region comprises a portion of the semiconductor substrate extending to the top working surface.
Claims19
An integrated circuit comprising:
- a level-shift transistor including:
- a source region near a working top surface of a semiconductor substrate, the semiconductor substrate having a first conductivity type;
- a drain region near the working top surface and laterally offset from the source region;
- a drift region extending from the drain region toward the source region, the drift region having a second conductivity type, the drift region including a first resurf region within the drift region near the working top surface and having the first conductivity type;
- and
- a gate located above the working top surface and laterally between the source and drain regions;
- a high voltage region including:
- a first well region laterally offset from the drift region, the first well region having the second conductivity type;
- a high voltage interconnect coupling the level-shift transistor to the high voltage region;
- and
- an isolation region located laterally between the level-shift transistor and the high voltage region, the isolation region comprising a portion of the semiconductor substrate extending to the top working surface.
A semiconductor device comprising:
- a semiconductor substrate having a first conductivity type;
- a first well in the semiconductor substrate, the first well having the second conductivity type, wherein the first well includes a drift region of a level-shift transistor, the drift region laterally separated from a high voltage isolation island region by an isolation region comprising a portion of the semiconductor substrate extending to a top working surface of the semiconductor substrate;
- a second well near the working top surface in the first well and having the first conductivity type, wherein the second well forms a resurf structure for the drift region and a resurf structure around a perimeter of the high voltage isolation island region;
- and
- a high voltage interconnect above the working top surface of the semiconductor substrate and coupling the drift region to the high voltage isolation island region.
Dependencies are inferred from the claim text.