Semiconductor device
AssigneePanasonic Corporation
InventorsMakoto Tsutsue, Masaki Utsumi
Life of this patent
Estimating the term…
Abstract
A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.
Claims22
A semiconductor device, comprising:
- a substrate including a chip region;
- a plurality of dielectric films formed on the substrate;
- seal rings formed in a peripheral part of the chip region, the seal rings including a first seal ring and a second seal ring both provided through the plurality of dielectric films in the peripheral part of the chip region;
- a protection film formed on a first dielectric film which is an uppermost film among the plurality of dielectric films;
- a first opening provided in the protection film and formed on the first seal ring;
- and
- a cap layer disposed in the first opening and in contact with the first seal ring, wherein:
- the first seal ring is disposed outside of the second seal ring and surrounds the second seal ring,
- an entirety of an upper surface of the second seal ring is covered by the protection film,
- a width of the first opening is larger than a width of the first seal ring formed in the first dielectric film, and both of side surfaces of the first opening are disposed on a region other than an upper surface of the first seal ring, and
- a thickness of a center of the cap layer in a depth direction is larger than a thickness of the protection film in the depth direction.
A semiconductor device, comprising:
- a substrate including a chip region;
- a plurality of dielectric films formed on the substrate;
- seal rings formed in a peripheral part of a chip region, the seal rings including a first seal ring and a second seal ring, the first seal ring surrounding the second seal ring, the first seal ring and second seal ring both provided through the plurality of dielectric films in the peripheral part of the chip region;
- a protection film formed on a first dielectric film, the first dielectric film being an uppermost film among the plurality of dielectric films;
- a first opening provided in the protection film and formed on the first seal ring;
- a cap layer disposed in the first opening and in contact with the first seal ring;
- and
- an interconnect formed in the first dielectric film in the chip region,
- wherein a width of the first opening is larger than a width of the first seal ring formed in the first dielectric film, and both of side surfaces of the first opening are disposed on a region other than an upper surface of the first seal ring, and
- a thickness of a center of the cap layer in a depth direction is larger than a thickness of the protection film in the depth direction.
Dependencies are inferred from the claim text.