US 8,618,617 B2Granted

Field effect transistor device

AssigneesInternational Business Machines Corporation, Globalfoundries Inc.

InventorsKevin K. Chan, Abhishek Dube, Eric C. Harley, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman, Linda R. Black

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Abstract

A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material.

Claims9

Dependent claims

A field effect transistor device comprising:

a gate stack portion disposed on a substrate;
a first cavity region in the substrate arranged on a first side of the gate stack portion;
a second cavity region in the substrate arranged on a second side of the gate stack portion;
a first epitaxially grown silicon material disposed in the first cavity region and the second cavity region, the first epitaxially grown silicon material including a void that exposes a portion of the substrate and defines two stress regions, the two stress regions being separated from one another by a second epitaxially grown silicon material different from the first epitaxially grown material;
wherein the two separate stress regions are formed at opposing sides of the void;
and
the second epitaxially grown silicon material is disposed in the first cavity region and the second cavity region, the second epitaxially grown silicon material in contact with the first epitaxially grown silicon material.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/783,526Filed 4 Mar 2013 · division
Priority: 29 Jun 2010
Published: US 2013/0175547 A111 Jul 2013
Granted: 31 Dec 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…
H10D 30/0323
Comprising silicon, e.g. amorphous silicon or polysilicon: comprising monocrystalline silicon
H10D 30/6713
Having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device:…

Family

Application12/825,791Parent of this division · filed 29 Jun 2010
US 2013/0175547 A1Pre-grant publication · published 11 Jul 2013
US 8,492,234 B2Parent of this division
US 2011/0316046 A1Published application
US 8,618,617 B2This patent

From the US filing history. Foreign family members aren’t listed.