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US 8,618,612 B2Granted
Integrated circuits based on aligned nanotubes
AssigneeUniversity of Southern California
InventorsChongwu Zhou, Koungmin Ryu, Alexander Badmaev, Chuan Wang
Life of this patent
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Abstract
Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.
Claims4
An apparatus, comprising at least one of:
- submicron back-gated nanotube transistors fabricated on aligned nanotubes with SiO2 as a gate dielectric and Si as a back-gate;
- submicron top-gated nanotube transistors on aligned nanotubes with high-k Al2O3 or HfO2 as a gate dielectric and a metal electrode as atop-gate at a wafer-scale;
- or
- submicron individual back-gated nanotube transistors on aligned nanotubes with high-k Al2O3 or HfO2 as a back-gate dielectric and a metal electrode as an individual back-gate.
1 more element
An apparatus, comprising:
- a wafer comprising at least one of the following:
- submicron back-gated nanotube transistors fabricated on aligned nanotubes with SiO2 as a gate dielectric and Si as a back-gate;
- submicron top-gated nanotube transistors on aligned nanotubes with high-k Al2O3 or HfO2 as a gate dielectric and a metal electrode as atop-gate at a wafer-scale;
- or
- submicron individual back-gated nanotube transistors on aligned nanotubes with high-k Al2O3 or HfO2 as a back-gate dielectric and a metal electrode as an individual back-gate.
2 more elements
Dependencies are inferred from the claim text.