Apparatus for improving multi-gate device performance
AssigneeIntel Corporation
InventorsBrian Doyle, Titash Rakshit, Jack Kavalieros
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Abstract
Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.
Claims16
A non-planar transistor device, comprising:
- a source landing pad and a drain landing pad;
- a shallow trench region adjacent to the source landing pad and the drain landing pad;
- a plurality of multi-gate fins, wherein each multi-gate fin comprises a plurality of gates, connected to the source landing pad and the drain landing pad, wherein the multi-gate fins are separated by a number of isolated regions;
- and
- a gate stack positioned between the source landing pad and the drain landing pad, in contact with the plurality of multi-gate fins, and on the isolation regions, wherein the gate stack comprises a gate dielectric and a gate electrode, wherein the gate dielectric extends across the isolated region between at least two multi-gate fins.
A non-planar dogbone transistor device comprising a plurality of tri-gate fins positioned between a source landing pad and a drain landing pad, wherein the tri-gate fins are connected to the source landing pad and the drain landing pad and a gate length of the tri-gate fins is substantially equal to a thickness of the source landing pad and the drain landing pad;
- isolated regions positioned between each of the tri-gate fins and between the source landing pad and the drain landing pad;
- and a gate stack connected to each gate of the tri-gate fins and on the isolated regions, wherein the gate stack is positioned between the source landing pad and the drain landing pad, and wherein the gate stack comprises a gate dielectric and a gate electrode, wherein the gate dielectric extends across the isolated region between at least two multi-gate fins.
A non-planar transistor device formed by the method, comprising:
- forming a plurality of multi-gate fins by depositing a barrier layer over a diffused body and a first sacrificial gate, polishing the barrier layer to expose the first sacrificial gate, removing the first sacrificial gate to expose a portion of the diffused body, forming a second sacrificial gate over the portion of the diffused body, forming a multi-fin mask over the diffused body, and etching the second sacrificial gate and diffused body through the multi-fin mask;
- forming isolation regions adjacent to the plurality of multi-gate fins;
- and
- forming a gate stack on the isolation regions and the plurality of multi-gate fins.
Dependencies are inferred from the claim text.