US 8,618,586 B2Granted

Memory device, semiconductor device, and electronic device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsJun Koyama, Shunpei Yamazaki

Life of this patent

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Abstract

An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

Claims18

Dependent claims

A semiconductor device comprising:

a first logic element;
a second logic element;
a third logic element;
a first transistor comprising a first terminal, a second terminal, and a gate;
a second transistor comprising a first terminal, a second terminal, and a gate;
a third transistor comprising a first terminal, a second terminal, and a gate;
a fourth transistor comprising a first terminal, a second terminal, and a gate;
a fifth transistor comprising a first terminal, a second terminal, and a gate;
and
a capacitor,
wherein:
an input terminal of the first logic element is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor,
an output terminal of the first logic element is electrically connected to an input terminal of the second logic element and the first terminal of the third transistor,
an output terminal of the second logic element is electrically connected to the second terminal of the second transistor,
the second terminal of the third transistor is electrically connected to the first terminal of the fifth transistor,
the second terminal of the fifth transistor is electrically connected to an output terminal of the third logic element,
an input terminal of the third logic element is electrically connected to the second terminal of the fourth transistor and the capacitor,
the first terminal of the fourth transistor is electrically connected to the first terminal of the first transistor, and
a channel formation region of the fourth transistor comprises an oxide semiconductor comprising at least In and Zn.

16 more elements

A semiconductor device comprising:

a first logic element;
a second logic element;
a third logic element;
a first transistor comprising a first terminal, a second terminal, and a gate;
a second transistor comprising a first terminal, a second terminal, and a gate;
a third transistor comprising a first terminal, a second terminal, and a gate;
a fourth transistor comprising a first terminal, a second terminal, and a gate;
a fifth transistor comprising a first terminal, a second terminal, and a gate;
and
a capacitor,
wherein:
an input terminal of the first logic element is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor,
an output terminal of the first logic element is electrically connected to an input terminal of the second logic element and the first terminal of the third transistor,
an output terminal of the second logic element is electrically connected to the second terminal of the second transistor,
the second terminal of the third transistor is electrically connected to the first terminal of the fifth transistor,
the second terminal of the fifth transistor is electrically connected to an output terminal of the third logic element,
an input terminal of the third logic element is electrically connected to the second terminal of the fourth transistor and the capacitor,
the first terminal of the fourth transistor is electrically connected to the first terminal of the first transistor, and
a channel formation region of the fourth transistor comprises an oxide semiconductor comprising at least In and Zn, and
a hydrogen concentration in the channel formation region is lower than or equal to 5×1019/cm3.

17 more elements

A semiconductor device comprising:

a first logic element;
a second logic element;
a third logic element;
a first transistor comprising a first terminal, a second terminal, and a gate;
a second transistor comprising a first terminal, a second terminal, and a gate;
a third transistor comprising a first terminal, a second terminal, and a gate;
a fourth transistor comprising a first terminal, a second terminal, and a gate;
a fifth transistor comprising a first terminal, a second terminal, and a gate;
and
a capacitor,
wherein:
an input terminal of the first logic element is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor,
an output terminal of the first logic element is electrically connected to an input terminal of the second logic element and the first terminal of the third transistor,
an output terminal of the second logic element is electrically connected to the second terminal of the second transistor,
the second terminal of the third transistor is electrically connected to the first terminal of the fifth transistor,
the second terminal of the fifth transistor is electrically connected to an output terminal of the third logic element,
an input terminal of the third logic element is electrically connected to the second terminal of the fourth transistor and the capacitor,
the first terminal of the fourth transistor is electrically connected to the first terminal of the first transistor,
a channel formation region of the fourth transistor comprises an oxide semiconductor comprising at least In Zn, and
the channel formation region of the fourth transistor further comprises crystals which are c-axis-oriented in a direction generally perpendicular to a surface of the oxide semiconductor.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/744,860Filed 18 Jan 2013 · continuation
Priority: JP 2009-29398225 Dec 2009
Published: US 2013/0127497 A123 May 2013
Granted: 31 Dec 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G06F 1/206
Cooling means: comprising thermal management
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
H03K 19/094
Using semiconductor devices: using field-effect transistors

Family

Application12/976,206Parent of this continuation · filed 22 Dec 2010
US 2013/0127497 A1Pre-grant publication · published 23 May 2013
US 2011/0156024 A1Published application
US 8,362,538 B2Related patent
US 8,618,586 B2This patent

From the US filing history. Foreign family members aren’t listed.