Thin film transistor array panel with overlapping floating electrodes and pixel electrodes
AssigneeSamsung Display Co., Ltd.
InventorJong-woong Chang
Life of this patent
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Abstract
According to an embodiment of the present invention, a thin film transistor array panel includes a gate line and a data line insulated from each other an insulating substrate where the gate line and the data line cross each other to define a pixel region, a thin film transistor (TFT) disposed at an intersection of the gate line and the data line, a floating electrode where at least a portion of the floating electrode overlaps the data line, and a pixel electrode disposed at the pixel region where the pixel electrode is connected to the TFT and overlaps the at least a portion of the floating electrode.
Claims15
A thin film transistor (TFT) array panel, comprising:
- a gate line and a data line insulated from each other on an insulating substrate;
- at least two pixel electrodes;
- at least one thin film transistor (TFT) including a gate electrode, a source electrode and a drain electrode respectively, wherein the gate electrode is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to one of the pixel electrodes;
- and
- a capacitive electrode, at least a portion of the capacitive electrode overlapping and oriented substantially parallel with the data line, wherein the capacitive electrode overlaps the pixel electrodes, and the capacitive electrode is without an opening or a slit facing the data line;
- a storage line which is at least approximately parallel with the gate line;
- and
- a drain extension portion extending from the drain electrode, wherein the storage line overlaps the drain extension portion
- wherein one of the pixel electrodes is disposed adjacent to a first side of the data line and another one of the pixel electrodes is disposed adjacent to a second side of the data line that is opposite to the first side.
A thin film transistor (TFT) array panel, comprising:
- a gate line and a data line insulated from each other on an insulating substrate;
- at least two pixel electrodes;
- at least one thin film transistor (TFT) including a gate electrode, a source electrode and a drain electrode respectively, wherein the gate electrode is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to one of the pixel electrodes;
- and
- a capacitive electrode, at least a portion of the capacitive electrode overlapping and oriented substantially parallel with the data line, wherein the capacitive electrode overlaps the pixel electrodes, and the capacitive electrode is without an opening or a slit facing the data line;
- a storage line which is at least approximately parallel with the gate line;
- and
- a contact hole formed on the storage line,
- wherein the drain electrode is connected to one of the pixel electrodes via the contact hole, and
- wherein one of the pixel electrodes is disposed adjacent to a first side of the data line and another one of the pixel electrodes is disposed adjacent to a second side of the data line that is opposite to the first side.
Dependencies are inferred from the claim text.