Liner property improvement
AssigneeApplied Materials, Inc.
InventorsKedar Sapre, Manuel Hernandez, Lei Luo
Life of this patent
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Abstract
Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 μm. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall.
Claims20
A method of processing a semiconductor substrate having a field region and at least one via defined by sidewalls and having a depth greater than 1 μm, the method comprising:
- depositing a lining layer comprising silicon, oxygen, and phosphorus and having a varying thickness of between about 50 nm and about 500 nm along the sidewalls of the via such that a first thickness of the liner layer at an upper portion of the via sidewall is less than about 5 times a second thickness of the liner layer at a lower portion of the via sidewall.
A method of forming a through-silicon via structure (TSV) on a semiconductor substrate, the method comprising:
- providing the semiconductor substrate having a plurality of transistors with a minimum feature size formed thereon and at least one via defined by sidewalls, the at least one via having a width that is at least two orders of magnitude greater than the minimum feature size of the transistors and a depth that is at least three orders of magnitude greater than the minimum feature size;
- and
- depositing a lining layer comprising silicon, oxygen, and phosphorus and having a varying thickness of between about 50 nm and about 500 nm along the sidewalls of the via such that a first thickness of the liner layer at an upper portion of the via sidewall is less than about 5 times a second thickness of the liner layer at a lower portion of the via sidewall.
Dependencies are inferred from the claim text.